Non-volatile memory metadata protection

1 . A method of operating a non-volatile memory (NVM) device, the method comprising:

encoding, by a memory controller of the NVM device, first metadata bits for an erase sector of a memory cell array of the NVM device, comprising:

forming a first data frame by filling the first data frame with the first metadata bits and a first number of dummy bits; and

encoding the first data frame using a systematic error-correction code (ECC), wherein encoding the first data frame generates a first code word that includes the first data frame and first redundant bits for the first data frame;

writing, by the memory controller, the first metadata bits and the first redundant bits in the erase sector of the memory cell array;

reading out, by the memory controller, the first metadata bits and the first redundant bits stored in the erase sector; and

performing an ECC decoding process for a read-out first metadata bits, comprising:

forming a second data frame by filling the second data frame with the read-out first metadata bits, the first number of dummy bits, and a read-out first redundant bits;

computing, by the memory controller, a syndrome vector for the second data frame in accordance with the systematic error-correction code; and

in response to determining that the syndrome vector comprises a non-zero element, performing, by the memory controller, error correction for the second data frame to obtain decoded first metadata bits.

2 . The method of claim 1 , wherein the systematic error-correction code is the same error-correction code used for protecting data bits stored in the erase sector.

3 . The method of claim 1 , wherein the dummy bits comprise a pre- determined number of bits with a pre-determined bit pattern.

4 . The method of claim 1 , wherein the systematic error-correction code is a systematic Hamming code.

5 . A non-volatile memory (NVM) device comprising:

a memory cell array comprising a plurality of erase sectors, wherein each erase sector of the plurality of erase sectors is configured to store data bits and metadata bits of the each erase sector;

an array access circuit coupled to the memory cell array and configured to perform read or write operations on the memory cell array; and

a memory controller coupled to the memory cell array and the array access circuit, wherein the memory controller is configured to:

encode first metadata bits for a first erase sector of the memory cell array by:

forming a first data frame by filling the first data frame with the first metadata bits and a first number of dummy bits; and

encoding the first data frame using a systematic error-correction code (ECC), wherein encoding the first data frame generates a first code word that includes the first data frame and first redundant bits for the first data frame;

write the first metadata bits and the first redundant bits in the first erase sector of the memory cell array;

read out the first metadata bits and the first redundant bits stored in the first erase sector; and

perform an ECC decoding process for the read-out first metadata bits by:

forming a second data frame by filling the second data frame with the read-out first metadata bits, the first number of dummy bits, and the read-out first redundant bits;

computing a syndrome vector for the second data frame in accordance with the systematic error-correction code; and

in response to determining that the syndrome vector comprises a non-zero element, performing error correction for the second data frame to obtain decoded first metadata bits.

6 . The NVM device of claim 5 , wherein the dummy bits are all zeros or all ones.

7 . The NVM device of claim 5 , wherein the systematic error-correction code is a systematic Hamming code.

8 . The NVM device of claim 5 , wherein the first metadata bits comprise an Erase Power-Loss Indicator (EPLI) of the first erase sector, wherein the memory controller is further configured to, after performing the ECC decoding process, comparing the EPLI in the decoded first metadata bits with a pre-determined bit pattern for the EPLI.