Memory system and data rearrangement method
According to one embodiment, a controller includes a counter counting a number of accesses of data in a nonvolatile memory, in a first unit which is a unit of access to data from the host. The controller determines whether a received read command is a sequential read command or a random read command, increments a value of the counter, which corresponds to data specified by the received read command, when the received read command is the random read command, and in a process of moving first data of a first block to a second block, controls rearrangement of the first data of the first block to the second block based on the value of the counter when the first data has a size of the first unit and needs to be arranged across two pages in the second block.
1 . A memory system comprising:
a nonvolatile memory including a plurality of blocks each including a plurality of pages; and
a controller connectable with a host, and configured to control the nonvolatile memory, wherein
the controller includes a counter counting a number of accesses of data stored in the nonvolatile memory in a first unit, the first unit being a unit of access to data from the host, and
the controller is configured to:
determine whether a read command received from the host is a command for a sequential read or a random read;
increment a value of the counter, which corresponds to data specified by the read command, when the read command is the command for the random read; and
in a process of moving first data of a first block to a second block, determine, based on the value of the counter for the first data, whether the first data is to be rearranged across two pages in the second block or rearranged in one page in the second block.
2 . The memory system of claim 1 , wherein
the controller is further configured to generate a frame including user data received from the host and an error correction code for detecting and correcting an error of the user data, and write the frame to the nonvolatile memory, and
a length of the user data is the first unit.
3 . The memory system of claim 1 , wherein
the controller is further configured to generate a frame including user data received from the host and an error correction code for detecting and correcting an error of the user data, and write the frame to the nonvolatile memory, and
a length of the frame is not changed before and after the process of moving the first data of the first block to the second block.
4 . The memory system of claim 1 , wherein the controller is configured to
control arrangement of data to each block of the nonvolatile memory for each first number of pages among the plurality of pages included in each block, and
in a case where the first data has the smallest counter value among the data arranged in the first number of pages, control the rearrangement of the first data from the first block to the second block such that the first data with the smallest counter value among the first data to be arranged in the first number of pages is rearranged across two pages.
5 . The memory system of claim 1 , wherein the controller is configured to
control arrangement of data to each block of the nonvolatile memory for each first number of pages among the plurality of pages included in each block, and
in a case where the first data has a value of the counter is greater than or equal to a threshold value,
control the rearrangement of the first data from the first block to the second block such that the first data is not rearranged across two pages.
6 . The memory system of claim 1 , wherein the controller is configured to compare a first logical address indicative of a logical position of the nonvolatile memory specified by a first read command with a second logical address specified by a second read command subsequent with the first read command, and determine whether the first read command and the second read command are the commands for the sequential read or the random read.
7 . The memory system of claim 1 , wherein the controller is configured to
compare a first physical address with a second physical address, the first physical address being indicative of a physical position of the nonvolatile memory associated with a first logical address indicative of a logical position of the nonvolatile memory specified by a first read command, the second physical address being associated with a second logical address specified by a second read command subsequent with the first read command, and
determine whether the first read command and the second read command are the commands for the sequential read or the random read.
8 . The memory system of claim 1 , wherein the controller is configured to
generate each of a plurality of frames including user data received from the host and an error correction code for detecting and correcting an error of the user data, and write the plurality of frames to the nonvolatile memory, when receiving a write command from the host,
when the controller moves the first data from the first block to the second block by a first method, count the number of the accesses to the data by the counter, for each of a plurality of the frames stored in the second block,
when the controller moves the first data from the first block to the second block by a second method, count the number of the accesses to the data by the counter, for each of the first unit of the first data stored in the second block,
the first method makes a length of the frame of to be stored in the second block different from a length of the frame stored in the first block, a length of the error correction code included in the frame to be stored in the second block different from a length of the error correction code included in the frame stored in the first block, and a length of the user data included in the frame to be stored in the second block equal to a length of the user data included in the frame stored in the first block, and
the second method makes a length of the frame to be stored in the second block equal to a length of the frame stored in the first block, a length of the error correction code included in the frame to be stored in the second block different from a length of the error correction code included in the frame stored in the first block, and a length of the user data included in the frame to be stored in the second block different from a length of the user data included in the frame stored in the first block.
9 . The memory system of claim 8 , wherein the controller is configured to
control the rearrangement of the first data of the first block to the second block such that a frame including data in which a value of the counter is greater than or equal to a threshold value is not arranged across two pages, when the frame is generated in the first method, and
control the rearrangement of the first data of the first block to the second block such that two frames to which data with a value of the counter greater than or equal to a threshold value is distributed are not arranged on two separate pages, when the frame is generated in the second method.
10 . The memory system of claim 1 , wherein the controller is configured to
skip incrementing the value of the counter, when the read command is the command for the sequential read.
11 . A data rearrangement method executed by a controller connectable with a host, and configured to control a nonvolatile memory including a plurality of blocks each including a plurality of pages, the method comprising:
determining that a read command received from the host is the command for a random read;
in response to determining that the read command is the command for the random read, incrementing a value of a counter corresponding to data specified by the read command, of counters for counting a number of accesses of data stored in the nonvolatile memory for each access unit from the host or for each frame, the frame including user data received from the host and an error correction code for detecting and correcting an error of the user data; and
in a process of moving first data of a first block to a second block,
determining that, based on the value of the counter for the first data, the first data is to be rearranged across two pages in the second block; and
determining that, based on the value of the counter for the first data, the first data is to be rearranged across in one page in the second block.
12 . The method of claim 11 , further comprising:
generating a frame including user data received from the host and an error correction code for detecting and correcting an error of the user data; and
writing the frame to the nonvolatile memory, wherein
a length of the user data is the access unit.
13 . The method of claim 11 , further comprising:
generating a frame including user data received from the host and an error correction code for detecting and correcting an error of the user data; and
writing the frame to the nonvolatile memory, wherein
a length of the frame is not changed before and after the process of moving the first data of the first block to the second block.
14 . The method of claim 11 , further comprising:
controlling arrangement of the first data to each block of the nonvolatile memory for each first number of pages among the plurality of pages included in each block;
detecting that the first data has the smallest counter value among the data arranged in the first number of pages; and
in response to detecting that the first data has the smallest counter value among the data arranged in the first number of pages, controlling the rearrangement of the first data from the first block to the second block such that the first data is rearranged across two pages.
15 . The method of claim 11 , further comprising:
controlling arrangement of data to each block of the nonvolatile memory for each first number of pages among the plurality of pages included in each block;
detecting that the first data has a value of the counter is greater than or equal to a threshold value; and
in response to detecting that the first data has a value of the counter is greater than or equal to a threshold value, controlling the rearrangement of the first data from the first block to the second block such that the first data is not rearranged across two pages.
16 . The method of claim 11 , further comprising:
comparing a first logical address indicative of a logical position of the nonvolatile memory specified by a first read command with a second logical address specified by a second read command subsequent with the first read command; and
determining that the first read command and the second read command are the commands for the random read.
17 . The method of claim 11 , further comprising:
comparing a first physical address with a second physical address, the first physical address being indicative of a physical position of the nonvolatile memory associated with a first logical address indicative of a logical position of the nonvolatile memory specified by a first read command, the second physical address being associated with a second logical address specified by a second read command subsequent with the first read command; and
determining that the first read command and the second read command are the commands for the random read.
18 . The method of claim 11 , further comprising:
generating each of a plurality of frames including user data received from the host and an error correction code for detecting and correcting an error of the user data, and writing the plurality of frames to the nonvolatile memory;
in the first data moved from the first block to the second block by a first method, counting the number of the accesses to the data by the counter, for each of the frames of the second block; and
in the first data moved from the first block to the second block by a second method, counting the number of the accesses to the data by the counter, for each of the first unit, wherein
the first method makes a length of the frame of to be stored in the second block different from a length of the frame stored in the first block, a length of the error correction code included in the frame to be stored in the second block different from a length of the error correction code included in the frame stored in the first block, and a length of the user data included in the frame to be stored in the second block equal to a length of the user data included in the frame stored in the first block, and
the second method makes a length of the frame to be stored in the second block equal to a length of the frame stored in the first block, a length of the error correction code included in the frame to be stored in the second block different from a length of the error correction code included in the frame stored in the first block, and a length of the user data included in the frame to be stored in the second block different from a length of the user data included in the frame stored in the first block.
19 . The method of claim 18 , further comprising:
in generating the frame by the first method, controlling the rearrangement of the first data of the first block to the second block such that a frame including data in which a value of the counter is greater than or equal to a threshold value is not arranged across two pages; and
in generating the frame by the second method, controlling the rearrangement of the first data of the first block to the second block such that two frames to which data with a value of the counter greater than or equal to a threshold value is distributed are not arranged on two separate pages.
20 . The method of claim 11 , further comprising:
skipping incrementing the value of the counter, which corresponds to data specified by the read command, in response to determining that the read command is the command for a sequential read.