Devices using chiplet based storage architectures

1 . A device for implementing a storage architecture, comprising:

a front-end chip configured to perform first interfacing with a first device;

a plurality of back-end chips configured to perform second interfacing with second devices; and

a memory chip disposed to be physically separated from the front-end chip and the plurality of back-end chips and configured to perform a communication with the front-end chip,

wherein the front-end chip, the plurality of back-end chips and the memory chip are disposed on a same package substrate, and each of the plurality of back-end chips is configured to output a control signal for controlling the second devices that are disposed outside of the package substrate.

2 . The device for the storage architecture of claim 1 , wherein the front-end chip, the plurality of back-end chips and the memory chip are configured in a chiplet structure in which the front-end chip, the plurality of back-end chips and the memory chip are physically separated to function independently of each other.

3 . The device for the storage architecture of claim 1 , wherein the front-end chip, the plurality of back-end chips and the memory chip are configured to be independently replaceable in response to any changes in a specification of at least one of the first device and the second devices.

4 . The device for the storage architecture of claim 1 , wherein the front-end chip is configured to communicate with the first device through a first interface standard and communicate with the memory chip through a second interface standard.

5 . The device for the storage architecture of claim 4 , wherein the front-end chip is configured to communicate with the plurality of back-end chips through the second interface standard.

6 . The device for the storage architecture of claim 4 , wherein the first interface standard is a compute express link (CXL) standard or a peripheral component interconnect express (PCIe) standard, and the second interface standard is universal chiplet interconnect express (UCIe) standard.

7 . The device for the storage architecture of claim 1 , wherein the memory chip includes a logic circuit configured to detect and correct an error when reading a data stored in the memory chip.

8 . The device for the storage architecture of claim 1 , wherein the first device is a host device, and the second devices are memory devices.

9 . The device for the storage architecture of claim 1 , wherein each of the second devices includes at least one of a volatile memory device, a non-volatile memory device, or an accelerator memory device.

10 . The device for the storage architecture of claim 1 , wherein the front-end chip is configured to communicate with a first memory device, and the plurality of back-end chips are configured to communicate with a second memory device, and a type of the first memory device is different from a type of the second memory device.

11 . A device for implementing a storage architecture, comprising:

at least one memory device disposed on a substrate; and

a controller package located on the substrate, and configured to control the at least one memory device,

wherein the controller package comprises,

a front-end chip configured to perform a communication with a host device,

at least one back-end chip configured to perform a communication with the at least one memory device, and the at least one memory device is disposed outside of the controller package; and

a memory chip disposed to be physically separated from the front-end chip and the at least one back-end chip and configured to perform a communication with the front-end chip,

wherein the front-end chip, at least one back-end chip and the memory chip are disposed on a same package substrate, and the at least one back-end chip outputs a control signal for controlling the at least one memory device.

12 . The device for the storage architecture of claim 11 , wherein the front-end chip is configured to communicate with the host device through a first interface standard and communicate with the memory chip through a second interface standard.

13 . The device for the storage architecture of claim 12 , wherein the front-end chip is configured to communicate with the at least one back-end chip through the second interface standard.

14 . The device for the storage architecture of claim 12 , wherein the first interface standard is a compute express link (CXL) standard or a peripheral component interconnect express (PCIe) standard, and the second interface standard is universal chiplet interconnect express (UCIe) standard.