Fault-tolerant hashing control architecture

Inventors: Haipeng Yan (Aurora, CA); Afshin Rezayee (Richmond Hill, CA); Vikram Suresh (Portland, OR); Malcolm Smith (Toronto, CA)

Assignee: Block, Inc.

G06F11/203 G06F11/2092 G06F13/4247

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Quick Facts

Patent No.: US 12705148
App. No.: 18/620,153
Granted: Aug 11, 2026
Kind: B1

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

Systems and methods are disclosed for fault-tolerant hash control. In some examples, a hashing system receives a dataset. The controller apportions hashing calculations across hashing chips to calculate at least one hash digest based on the dataset. The hashing chips include at least a first hashing chip, a second hashing chip, and a third hashing chip. A first connector couples the first hashing chip to the second hashing chip. A second connector couples the second hashing chip to the third hashing chip. A backup connector couples the first hashing chip to the third hashing chip, bypassing the second hashing chip. The first hashing chip sends a communication to the third hashing chip along the backup connector that bypasses the second hashing chip in response to a determination that the second hashing chip is nonresponsive.

Claims (32)

1 . A system for hashing management, the system comprising:

a circuit board;

a controller that receives at least one dataset;

a plurality of hashing chips on the circuit board, wherein the plurality of hashing chips are coupled to one another and to the controller using a plurality of connectors on the circuit board, wherein the controller sends a plurality of hashing communications to the plurality of hashing chips to apportion hashing calculations across the plurality of hashing chips and to calculate at least one hash digest based on the at least one dataset, wherein the plurality of hashing chips includes at least a first hashing chip and a second hashing chip and a third hashing chip; and

the plurality of connectors, wherein the first hashing chip is coupled to the second hashing chip using at least a first connector of the plurality of connectors, wherein the second hashing chip is coupled to the third hashing chip using at least a second connector of the plurality of connectors, and wherein the first hashing chip is coupled to the third hashing chip using at least a backup connector of the plurality of connectors that bypasses the second hashing chip, wherein the backup connector is automatically activated and the first connector and the second connector are automatically deactivated in response to a determination that the second hashing chip is nonresponsive to a first hashing communication, the first hashing communication sent from the controller toward the second hashing chip through the first hashing chip and the first connector, wherein a second hashing communication is conveyed between the first hashing chip and the third hashing chip through the backup connector while the backup connector is activated, and wherein the plurality of hashing communications include the first hashing communication and the second hashing communication.

2 . The system of claim 1 , wherein the controller instructs the first hashing chip to send the first hashing communication along the first connector, and wherein the controller instructs the first hashing chip to send the second hashing communication along the backup connector.

3 . The system of claim 1 , wherein the first hashing chip is connected to the second hashing chip using at least the first connector as part of a daisy chain, wherein the second hashing chip is connected to the third hashing chip using at least the second connector as part of the daisy chain, and wherein the backup connector bypasses a portion of the daisy chain that includes at least the second hashing chip, the first connector, and the second connector.

4 . A system, the system comprising:

a circuit board;

a controller that receives at least one dataset; and

a plurality of hashing chips on the circuit board, wherein the plurality of hashing chips are coupled to one another and to the controller, wherein the controller sends a plurality of hashing communications to the plurality of hashing chips to apportion hashing calculations across the plurality of hashing chips to calculate at least one hash digest based on the at least one dataset, wherein the plurality of hashing chips includes at least a first hashing chip and a second hashing chip and a third hashing chip, wherein a backup connector is automatically activated and a first connector is automatically deactivated in response to a determination that the second hashing chip is nonresponsive to a first hashing communication, the first hashing communication sent from the controller toward the second hashing chip through the first hashing chip and the first connector, wherein a second hashing communication is conveyed between the first hashing chip and the third hashing chip through the backup connector while the backup connector is activated, and wherein the plurality of hashing communications include the first hashing communication and the second hashing communication.

5 . The system of claim 4 , wherein the first hashing chip is coupled to the second hashing chip using at least the first connector, wherein the second hashing chip is coupled to the third hashing chip using at least a second connector that is deactivated in response to the determination that the second hashing chip is nonresponsive to the first hashing communication, and wherein the first hashing chip is coupled to the third hashing chip using at least the backup connector that bypasses the second hashing chip.

6 . The system of claim 4 , wherein the first hashing chip is connected to the second hashing chip using the first connector, wherein the second hashing chip is connected to the third hashing chip using a second connector that is deactivated in response to the determination that the second hashing chip is nonresponsive to the first hashing communication, and wherein the first hashing chip is connected to the third hashing chip using the backup connector that bypasses the second hashing chip.

7 . The system of claim 4 , wherein the first hashing chip is connected to the second hashing chip using at least the first connector as part of a daisy chain, wherein the second hashing chip is connected to the third hashing chip using at least a second connector as part of the daisy chain, and wherein the backup connector bypasses a portion of the daisy chain that includes at least the second hashing chip, the first connector, and the second connector.

8 . The system of claim 4 , wherein each hashing chip of the plurality of hashing chips is connected as part of a daisy chain that includes the first connector and a second connector that couples the second hashing chip to the third hashing chip.

9 . The system of claim 7 , wherein each hashing chip of the plurality of hashing chips is connected to one of a plurality of backup connectors, wherein each of the plurality of backup connectors bypasses at least one of the plurality of hashing chips in the daisy chain, and wherein the plurality of backup connectors includes the backup connector that bypasses the second hashing chip.

10 . The system of claim 7 , wherein each hashing chip of the plurality of hashing chips includes a first input contact and a second input contact, wherein the first input contact is coupled to at least a portion of the daisy chain, wherein the second input contact is coupled to one of a plurality of backup connectors that bypasses one of the plurality of hashing chips in the daisy chain, and wherein the plurality of backup connectors includes the backup connector that bypasses the second hashing chip.

11 . The system of claim 4 , wherein the controller instructs the first hashing chip to send the first hashing communication along the first connector, and wherein the controller instructs the first hashing chip to send the second hashing communication to the third hashing chip along the backup connector.

12 . The system of claim 4 , wherein the determination that the second hashing chip is nonresponsive is made at least in part by the controller.

13 . The system of claim 4 , wherein the determination that the second hashing chip is nonresponsive is made at least in part by the first hashing chip.

14 . The system of claim 4 , wherein the plurality of hashing chips are coupled to one another using a plurality of unidirectional connectors.

15 . The system of claim 4 , wherein the plurality of hashing chips are coupled to one another using a plurality of bidirectional connectors.

16 . The system of claim 4 , wherein the controller directly connects to one hashing chip of the plurality of hashing chips, and wherein the controller communicates with the plurality of hashing chips through the one hashing chip.

17 . The system of claim 4 , wherein the controller directly connects to at least two hashing chips of the plurality of hashing chips, and wherein the controller communicates with the plurality of hashing chips through at least one of the at least two hashing chips.

18 . The system of claim 4 , wherein at least a portion of the plurality of hashing chips are organized in a tree arrangement of the plurality of hashing chips, wherein the tree arrangement includes a hub configured to convey data from a parent node hashing chip to a set of child node hashing chips, wherein the plurality of hashing chips includes the parent node hashing chip and the set of child node hashing chips.

19 . The system of claim 4 , wherein the second hashing communication includes at least one of an instruction or a hash digest, wherein the instruction is from the controller and instructs how at least a subset of the hashing calculations are to be apportioned across the plurality of hashing chips, wherein the hash digest is generated by one of the plurality of hashing chips via one of the hashing calculations.

20 . A method of hashing management, the method comprising:

receive at least one dataset;

apportion hashing calculations for hashing the at least one dataset among a plurality of hashing chips on a circuit board via a plurality of hashing communications sent to the plurality of hashing chips, wherein the plurality of hashing chips includes at least a first hashing chip and a second hashing chip and a third hashing chip, wherein the first hashing chip is coupled to the second hashing chip using at least a first connector, wherein the second hashing chip is coupled to the third hashing chip using at least a second connector, and wherein the first hashing chip is coupled to the third hashing chip using at least a backup connector that bypasses the second hashing chip;

determining that the second hashing chip is nonresponsive to a first hashing communication of the plurality of hashing communications;

activating the backup connector, and deactivating the first connector and the second connector, in response to determining that the second hashing chip is nonresponsive; and

conveying a second hashing communication of the plurality of hashing communications between the first hashing chip and the third hashing chip along the backup connector while the backup connector is activated, wherein the first connector, the second connector, and the backup connector are on the circuit board.