Non-intrusive processor instrumentation

1 . A system for non-intrusive processor instrumentation, comprising:

one or more hardware processors configured to execute a software program, wherein at least one hardware processor of the one or more hardware processors comprises:

at least one internal component having state information not stored in a register file of the at least one hardware processor; and

sampler circuitry connected to the at least one internal component and configured to sample a plurality of processor internal values, including the state information of the at least one internal component, where each processor internal value is a value of one of a plurality of processor state elements, without interrupting execution of the software program; and

at least one collector circuitry coupled to the sampler circuitry, configured to receive the plurality of processor internal values from the sampler circuitry and process the plurality of processor internal values while the one or more hardware processors continue normal operation.

2 . The system of claim 1 , wherein the plurality of processor internal values comprises at least one internal state value of at least one processor component of the at least one hardware processor.

3 . The system of claim 2 , wherein the at least one processor component includes at least one of: a prefetch buffer, a Branch Prediction Unit (BPU), a pipeline management circuitry, a cache controller, an Instruction Fetch Unit (IFU), a microcode cache, and a memory subsystem.

4 . The system of claim 2 , wherein the at least one internal state value is not accessible via a register file of the at least one hardware processor.

5 . The system of claim 1 , wherein the plurality of processor internal values comprises a copy of at least part of a register file of the at least one hardware processor.

6 . The system of claim 1 , wherein the sampler circuitry is configurable to control when to sample the plurality of processor internal values based on at least one of: a periodic clock cycle, an identified program counter value, or a trigger instruction in the software program.

7 . The system of claim 1 , wherein the at least one collector circuitry is configured to:

perform an analysis of the plurality of processor internal values; and

store an outcome of the analysis.

8 . The system of claim 7 , wherein the analysis includes calculating at least one of: an average value of a plurality of processor internal values collected over time, a minimum value of a plurality of processor internal values collected over time, or a maximum value of a plurality of processor internal values collected over time.

9 . The system of claim 1 , further comprising a management component configured to receive processed data from the at least one collector circuitry and perform another analysis of the processed data.

10 . The system of claim 9 , wherein the management component computes an optimized software program using an outcome of the other analysis, improving at least one performance metric of executing the software program.

11 . The system of claim 1 , wherein the sampler circuitry is further configured to send an event indicator.

12 . A method for non-intrusive processor instrumentation, comprising:

executing a software program by one or more hardware processors, wherein at least one hardware processor of the one or more hardware processors comprises at least one internal component having state information not stored in a register file of the at least one hardware processor, and sampler circuitry integrated within the at least one hardware processor and connected to the at least one internal component;

sampling, by the sampler circuitry, a plurality of processor internal values, including the state information of the at least one internal component, without interrupting execution of the software program, where each processor internal value of the plurality of processor internal values is a value of one of a plurality of processor state elements;

receiving, by at least one collector circuitry coupled to the sampler circuitry, the plurality of processor internal values from the sampler circuitry; and

processing, by the at least one collector circuitry, the plurality of processor internal values while the one or more hardware processors continue normal operation.

13 . The method of claim 12 , wherein sampling the plurality of processor internal values occurs asynchronously to the execution of the software program.

14 . The method of claim 12 , further comprising configuring the sampler circuitry to control when to sample the plurality of processor internal values based on at least one of: a periodic clock cycle, an identified program counter value, or a trigger instruction in the software program.

15 . The method of claim 12 , wherein processing the plurality of processor internal values comprises performing an analysis to reduce storage space requirements.

16 . The method of claim 12 , further comprising providing processed data from the at least one collector circuitry to a management component for optimization of the software program.

17 . A processor comprising:

execution circuitry configured to execute instructions of a software program;

a register file accessible to the execution circuitry;

at least one internal component having state information not stored in the register file; and

sampler circuitry, integrated within the processor, connected to the at least one internal component, and configured to sample a plurality of processor internal values, where each processor internal value is a value of one of a plurality of processor state elements, including values from the register file and the state information of the at least one internal component without interrupting operation of the execution circuitry, and configured to be coupled to at least one collector circuitry, where the at least one collector circuitry is configured to receive and process the plurality of processor internal values while the execution circuitry continues to execute the instructions.

18 . The processor of claim 17 , wherein the sampler circuitry is configured to operate asynchronously to the execution circuitry.

19 . The processor of claim 17 , wherein the plurality of processor internal values comprises state information of at least one of: a prefetch buffer, a Branch Prediction Unit (BPU), a pipeline management circuitry, a cache controller, an Instruction Fetch Unit (IFU), a microcode cache, and a memory subsystem.

20 . The processor of claim 17 , wherein the sampler circuitry is configurable to sample the plurality of processor internal values based on at least one of: a periodic clock cycle, an identified program counter value, or an instruction in the software program.

21 . A software program product for non-intrusive processor instrumentation comprises:

a non-transitory computer readable storage medium;

first program instructions for executing a software program by one or more hardware processors, where at least one of the one or more hardware processors comprises at least one internal component having state information not stored in a register file of the at least one hardware processor, and integrated sampler circuitry connected to the at least one internal component;

second program instructions for configuring the sampler circuitry to control sampling of a plurality of processor internal values, including the state information of the at least one internal component, without interrupting execution of the software program; and

third program instructions for analyzing, by at least one management component, processed data received from at least one collector circuitry, wherein the at least one collector circuitry is coupled to the sampler circuitry and configured to receive the plurality of processor internal values from the sampler circuitry;

wherein the first, second, and third program instructions are executed by at least one computerized processor from the non-transitory computer readable storage medium.