Watchpoints for debugging in a graphics environment

1 . A processor comprising:

processing resources to perform graphics operations using a plurality of threads; and

hardware circuitry coupled to the processing resources, the hardware circuitry comprising:

a watchpoint register programmed with a value of a watchpoint address, the watchpoint address comprising an address of a memory location in the processor; and

sequencer hardware circuitry to:

determine, using the watchpoint register, whether a memory access request received from a thread of the plurality of threads is requesting access to the watchpoint address; and

responsive to the memory access request requesting the access to the watchpoint address:

determine an access type of an operation that accesses the watchpoint address, wherein the access type comprises at least one of a store, load, or atomic;

determine, based on the access type of the operation, an address comparison technique to implement to make an address comparison corresponding to the watchpoint address; and

return, using the address comparison, an exception payload to the thread, the exception payload comprising watchpoint details corresponding to the watchpoint address and a scoreboard identifier (SBID) associated with the memory access request, wherein the SBID comprises a hardware data structure that logs and observes data dependencies of the memory access request in the processing resources, and wherein the exception payload is returned in response to the memory access request requesting the access to the watchpoint address using the access type indicated in an access type field of the watchpoint register.

2 . The processor of claim 1 , wherein the SBID is to track when registers used in the memory access request are available to use and is to relate the watchpoint address back to the thread and instruction issuing the memory access request.

3 . The processor of claim 1 , wherein the watchpoint address is provided by a debugging application to a debug surface corresponding to the processor.

4 . The processor of claim 3 , wherein an exception handling routine of the processor reads the watchpoint address from the debug surface and causes the watchpoint address to be stored to the watchpoint register.

5 . The processor of claim 1 , wherein the hardware circuitry is further to return a data payload in response to the memory access request.

6 . The processor of claim 1 , wherein, responsive to receiving the exception payload, the thread is to jump to an exception handling routine of the processor, the exception handling routine is to read the watchpoint details from a debug register corresponding to the thread, store the watchpoint details to a debug surface corresponding to the processor, and notify a debugger application via an interrupt process.

7 . The processor of claim 1 , wherein the processor comprises a graphics processing unit (GPU).

8 . The processor of claim 1 , wherein the processor is at least one of a single instruction multiple data (SIMD) machine or a single instruction multiple thread (SIMT) machine.

9 . A method comprising:

causing, by hardware circuitry of a processor, a watchpoint register of the hardware circuitry to be programmed with a value of a watchpoint address, the watchpoint address comprising an address of a memory location in the processor, wherein the processor comprises processing resources to perform graphics operations using a plurality of threads;

determining, by sequence hardware circuitry of the hardware circuitry based on the watchpoint register, whether a memory access request received from a thread of the plurality of threads is requesting access to the watchpoint address; and

responsive to the memory access request requesting the access to the watchpoint address:

determining an access type of an operation that accesses the watchpoint address, wherein the access type comprises at least one of a store, load, or atomic;

determining, based on the access type of the operation, an address comparison technique to implement to make an address comparison corresponding to the watchpoint address; and

returning, by the sequencer hardware circuitry using the address comparison, an exception payload to the thread, the exception payload comprising watchpoint details corresponding to the watchpoint address and a scoreboard identifier (SBID) associated with the memory access request, wherein the SBID comprises a hardware data structure that logs and observes data dependencies of the memory access request in the processing resources, and wherein the exception payload is returned in response to the memory access request requesting the access to the watchpoint address using the access type indicated in an access type field of the watchpoint register.

10 . The method of claim 9 , wherein the SBID is to track when registers used in the memory access request are available to use and is to relate the watchpoint address back to the thread and instruction issuing the memory access request.

11 . The method of claim 9 , wherein the watchpoint address is provided by a debugging application to a debug surface corresponding to the processor, and wherein an exception handling routine of the processor reads the watchpoint address from the debug surface and causes the watchpoint address to be stored to the watchpoint register.

12 . The method of claim 9 , further comprising returning, by the hardware circuitry, a data payload in response to the memory access request.

13 . The method of claim 9 , wherein, responsive to receiving the exception payload, the thread is to jump to an exception handling routine of the processor, the exception handling routine is to read the watchpoint details from a debug register corresponding to the thread, store the watchpoint details to a debug surface corresponding to the processor, and notify a debugger application via an interrupt process.

14 . A system comprising:

a memory to store a block of data; and

a processor coupled to the memory, the processor comprising:

processing resources to perform graphics operations using a plurality of threads; and

hardware circuitry coupled to the processing resources, the hardware circuitry comprising:

a watchpoint register programmed with a value of a watchpoint address, the watchpoint address comprising an address of a memory location in the processor; and

sequencer hardware circuitry to:

determine, using the watchpoint register, whether a memory access request received from a thread of the plurality of threads is requesting access to the watchpoint address; and

responsive to the memory access request requesting the access to the watchpoint address:

determine an access type of an operation that accesses the watchpoint address, wherein the access type comprises at least one of a store, load, or atomic;

determine, based on the access type of the operation, an address comparison technique to implement to make an address comparison corresponding to the watchpoint address; and

return, using the address comparison, an exception payload to the thread, the exception payload comprising watchpoint details corresponding to the watchpoint address and a scoreboard identifier (SBID) associated with the memory access request, wherein the SBID comprises a hardware data structure that logs and observes data dependencies of the memory access request in the processing resources, and wherein the exception payload is returned in response to the memory access request requesting the access to the watchpoint address using the access type indicated in an access type field of the watchpoint register.

15 . The system of claim 14 , wherein the SBID is to track when registers used in the memory access request are available to use and is to relate the watchpoint address back to the thread and instruction issuing the memory access request.

16 . The system of claim 14 , wherein the watchpoint address is provided by a debugging application to a debug surface corresponding to the processor, and wherein an exception handling routine of the processor reads the watchpoint address from the debug surface and causes the watchpoint address to be stored to the watchpoint register.

17 . The system of claim 14 , wherein, responsive to receiving the exception payload, the thread is to jump to an exception handling routine of the processor, the exception handling routine is to read the watchpoint details from a debug register corresponding to the thread, store the watchpoint details to a debug surface corresponding to the processor, and notify a debugger application via an interrupt process.

18 . A non-transitory computer-readable storage medium having stored thereon executable computer program instructions that, when executed by one or more processors, cause the one or more processors to perform operations comprising:

causing, by hardware circuitry of a processor of the one or more processors, a watchpoint register of the hardware circuitry to be programmed with a value of a watchpoint address, the watchpoint address comprising an address of a memory location in the processor, wherein the processor comprises processing resources to perform graphics operations using a plurality of threads;

determining, by sequencer hardware circuitry of the hardware circuitry based on the watchpoint register, whether a memory access request received from a thread of the plurality of threads is requesting access to the watchpoint address; and

responsive to the memory access request requesting the access to the watchpoint address:

determining an access type of an operation that accesses the watchpoint address, wherein the access type comprises at least one of a store, load, or atomic;

determining, based on the access type of the operation, an address comparison technique to implement to make an address comparison corresponding to the watchpoint address; and

returning, by the sequencer hardware circuitry using the address comparison, an exception payload to the thread, the exception payload comprising watchpoint details corresponding to the watchpoint address and a scoreboard identifier (SBID) associated with the memory access request, wherein the SBID comprises a hardware data structure that logs and observes data dependencies of the memory access request in the processing resources, and wherein the exception payload is returned in response to the memory access request requesting the access to the watchpoint address using the access type indicated in an access type field of the watchpoint register.

19 . The non-transitory computer-readable storage medium of claim 18 , wherein the SBID is to track when registers used in the memory access request are available to use and is to relate the watchpoint address back to the thread and instruction issuing the memory access request.

20 . The non-transitory computer-readable storage medium of claim 18 , wherein the watchpoint address is provided by a debugging application to a debug surface corresponding to the processor, and wherein an exception handling routine of the processor reads the watchpoint address from the debug surface and causes the watchpoint address to be stored to the watchpoint register.

21 . The non-transitory computer-readable storage medium of claim 18 , wherein, responsive to receiving the exception payload, the thread is to jump to an exception handling routine of the processor, the exception handling routine is to read the watchpoint details from a debug register corresponding to the thread, store the watchpoint details to a debug surface corresponding to the processor, and notify a debugger application via an interrupt process.