IP Library Granted Patent US 12705179
Granted Patent B2
US 12705179 · App. 18/786,600 · Granted Aug 11, 2026

Memory module, memory system including memory module, and method of operating the same

Inventor: Sung Woo Hyun (Gyeonggi-do, KR)
Assignee: SK hynix Inc.
G06F12/0862G06F12/12
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Quick Facts
Patent No.
US 12705179
App. No.
18/786,600
Granted
Aug 11, 2026
Kind
B2
Abstract

The present technology relates to an electronic device. According to the present technology, a memory module communicating with a host through a compute express link (CXL) interface includes a non-volatile memory device, a volatile memory device and a memory controller. The non-volatile memory device may store data. The memory controller may select candidate data to be prefetched among the data based on access pattern information of the host for the data and a plurality of algorithms, and prefetch target data among the candidate data to the volatile memory device.

Claims (12)

1 . A memory module communicating with a host through a compute express link (CXL) interface, the memory module comprising:

a non-volatile memory device configured to store data;

a volatile memory device; and

a memory controller configured to:

select a plurality of candidate data to be prefetched among the data based on access pattern information of the host for the data and a plurality of algorithms,; and

calculate a priority for the plurality of candidate data by applying a different weight to the plurality of algorithms;

select target data having a highest priority among the plurality of candidate data; and

prefetch the target data to the volatile memory device.

2 . The memory module of claim 1 , wherein the memory controller comprises:

a first controller configured to control the volatile memory device;

a second controller configured to control the non-volatile memory device; and

a processor configured to control data transmission between the host, the first controller, and the second controller, and prefetch the target data determined according to a prefetch priority of the plurality of candidate data calculated based on the plurality of algorithms and the access pattern information of the host from the non-volatile memory device to the volatile memory device.