Direct memory access data transfers
In various examples, systems and methods are disclosed that relate to linking and performing direct memory access (DMA) transfers. In one example, an accelerator can generate data associated with a descriptor that represents multiple DMA transfers associated with a plurality of DMA transfer types. The accelerator can provide the data associated with the descriptor to a device (or group of devices) involved in performing the DMA transfers as a set of linked DMA transfers. In response to receiving the data associated with the descriptor, the device(s) that receive the data associated with the descriptor can be configured to perform DMA transfers and allow for movement of the data specified by the descriptor to be moved from source memory to destination memory.
1 . One or more processors comprising:
one or more circuits to:
determine a first direct memory access (DMA) transfer associated with a first DMA transfer type based at least on generation of frame data associated with a frame obtained using at least one sensor;
determine at least one second DMA transfer associated with a second DMA transfer type based at least on the frame to be linked to the first DMA transfer, the first DMA transfer type associated with a first frame type and the second DMA transfer type associated with a second frame type different from the first frame type;
responsive to determining the at least one second DMA transfer, generate data associated with a descriptor based at least on linking the first DMA transfer and the at least one second DMA transfer for the frame; and
provide the data associated with the descriptor to a DMA system, the data associated with the descriptor configured to cause the DMA system to obtain the frame data associated with the frame from source memory in accordance with instructions represented by the descriptor and store the frame data in destination memory.
2 . The one or more processors of claim 1 , wherein the one or more circuits that determine the at least one second DMA transfer are to:
determine a sequence of DMA transfers to be performed using the DMA system based at least on the frame, and
wherein the one or more circuits that generate the data associated with the descriptor are to:
generate the data associated with the descriptor to cause the DMA system to perform the DMA transfers based at least on an amount of DMA transfers represented by the sequence of DMA transfers.
3 . The one or more processors of claim 2 , wherein the sequence of DMA transfers to be performed using the DMA system are associated with at least one image processing operation.
4 . The one or more processors of claim 1 , wherein the one or more circuits that determine the at least one second DMA transfer are to:
determine that a plurality of DMA transfers are to be performed based at least on the frame, and
wherein the one or more circuits that provide the data associated with the descriptor to the DMA system are to:
provide an indication that the plurality of DMA transfers are not complete.
5 . The one or more processors of claim 4 , wherein the plurality of DMA transfers are associated with one or more of: a prediction operation, an object tracking operation, or a trajectory prediction operation.
6 . The one or more processors of claim 4 , wherein the one or more circuits are to:
provide a second indication that a DMA transfer of the plurality of DMA transfers is a final DMA transfer to be performed for the descriptor.
7 . The one or more processors of claim 1 , wherein the descriptor comprises a first descriptor,
wherein the one or more circuits are to:
determine a third DMA transfer based at least on generation of second frame data associated with a second frame obtained using the at least one sensor;
determine at least one fourth DMA transfer based at least on the second frame; and
generate data associated with at least one second descriptor based at least on the third DMA transfer and the at least one fourth DMA transfer, and
wherein the data associated with the at least one second descriptor is configured to cause the DMA system to obtain the second frame data associated with the frame from source memory based at least on the descriptor performing one or more operations in accordance with the descriptor.
8 . The one or more processors of claim 7 , wherein the one or more circuits are to:
provide the data associated with the at least one second descriptor to the DMA system to configure the DMA system to perform the third DMA transfer and the at least one fourth DMA transfer as the first DMA transfer and the at least one second DMA transfer are performed by the DMA system.
9 . The one or more processors of claim 1 , wherein the one or more processors are comprised in at least one of:
a control system for an autonomous or semi-autonomous machine;
a perception system for an autonomous or semi-autonomous machine;
a system implemented using a robot;
an aerial system;
a medical system;
a boating system;
a smart area monitoring system;
a system for performing deep learning operations;
a system for performing simulation operations;
a system for generating or presenting virtual reality (VR) content, augmented reality (AR) content, or mixed reality (MR) content;
a system for performing digital twin operations;
a system implemented using an edge device;
a system incorporating one or more virtual machines (VMs);
a system for generating synthetic data;
a system implemented at least partially in a data center;
a system for performing conversational artificial intelligence (AI) operations;
a system for performing generative AI operations;
a system implementing language models;
a system for implementing vision language models (VLMs);
a system implementing large language models (LLMs);
a system for implementing multi-modal language models;
a system for hosting one or more real-time streaming applications;
a system for performing light transport simulation;
a system for performing collaborative content creation for 3D assets; or
a system implemented at least partially using cloud computing resources.
10 . A system, comprising:
at least one direct memory access (DMA) system configured to perform one or more operations involved in one or more DMA transfers; and
at least one accelerator configured to process data associated with one or more frames, the at least one accelerator comprising one or more circuits to:
determine a first DMA transfer associated with a first DMA transfer type based at least on generation of frame data associated with a frame as obtained using at least one sensor;
determine at least one second DMA transfer associated with a second DMA transfer type based at least on the frame to be linked to the first DMA transfer, the first DMA transfer type associated with a first frame type and the second DMA transfer type associated with a second frame type different from the first frame type;
responsive to determining the at least one second DMA transfer, generate data associated with a descriptor based at least on linking the first DMA transfer and the at least one second DMA transfer for the frame; and
provide the data associated with the descriptor to the DMA system, the data associated with the descriptor configured to cause the DMA system to obtain the frame data associated with the frame from source memory based at least on the descriptor and store the frame data in destination memory.
11 . The system of claim 10 , wherein the one or more circuits of the accelerator that determine the at least one second DMA transfer are to:
determine a sequence of DMA transfers to be performed by the DMA system based at least on the frame, and
wherein the one or more circuits of the accelerator that generate the data associated with the descriptor are to:
generate the data associated with the descriptor to cause the DMA system to perform the DMA transfers based at least on an amount of DMA transfers represented by the sequence of DMA transfers.
12 . The system of claim 11 , wherein the sequence of DMA transfers to be performed by the DMA system are associated with at least one image processing operation.
13 . The system of claim 10 , wherein the one or more circuits of the accelerator that determine the at least one second DMA transfer are to:
determine that a plurality of DMA transfers are to be performed based at least on the frame, and
wherein the one or more circuits of the accelerator that provide the data associated with the descriptor to the DMA system are to:
provide an indication that the plurality of DMA transfers are not complete.
14 . The system of claim 13 , wherein the plurality of DMA transfers are associated with one or more of: a prediction operation, an object tracking operation, or a trajectory prediction operation.
15 . The system of claim 13 , wherein the one or more circuits of the accelerator are to:
provide a second indication that a DMA transfer of the plurality of DMA transfers is a final DMA transfer to be performed for the descriptor.
16 . The system of claim 10 , wherein the descriptor comprises a first descriptor,
wherein the one or more circuits of the accelerator are to:
determine a third direct memory access (DMA) transfer based at least on generation of second frame data generated by a sensor, the frame data associated with a second frame;
determine at least one fourth DMA transfer based at least on the second frame; and
generate data associated with at least one second descriptor based at least on the third DMA transfer and the at least one fourth DMA transfer, and
wherein the data associated with the at least one second descriptor is configured to cause the DMA system to obtain the second frame data associated with the frame from source memory based at least on the descriptor performing one or more operations in accordance with the descriptor.
17 . The system of claim 16 , wherein the one or more circuits of the accelerator are to:
provide the data associated with the at least one second descriptor to the DMA system to configure the DMA system to perform the third DMA transfer and the at least one fourth DMA transfer as the first DMA transfer and the at least one second DMA transfer are performed by at least one device of the accelerator.
18 . The system of claim 10 , wherein the at least one DMA system or the at least one accelerator are comprised in at least one of:
a control system for an autonomous or semi-autonomous machine;
a perception system for an autonomous or semi-autonomous machine;
a system implemented using a robot;
an aerial system;
a medical system;
a boating system;
a smart area monitoring system;
a system for performing deep learning operations;
a system for performing simulation operations;
a system for generating or presenting virtual reality (VR) content, augmented reality (AR) content, or mixed reality (MR) content;
a system for performing digital twin operations;
a system implemented using an edge device;
a system incorporating one or more virtual machines (VMs);
a system for generating synthetic data;
a system implemented at least partially in a data center;
a system for performing conversational artificial intelligence (AI) operations;
a system for performing generative AI operations;
a system implementing language models;
a system for implementing vision language models (VLMs);
a system for implementing large language models (LLMs);
a system for implementing multi-modal language models;
a system for hosting one or more real-time streaming applications;
a system for performing light transport simulation;
a system for performing collaborative content creation for 3D assets; or
a system implemented at least partially using cloud computing resources.
19 . A method comprising:
determining a first direct memory access (DMA) transfer associated with a first DMA transfer type based at least on generation of frame data associated with a frame obtained using at least one sensor;
determining at least one second DMA transfer associated with a second DMA transfer type based at least on the frame, the first DMA transfer type associated with a first frame type and the second DMA transfer type associated with a second frame type different from the first frame type;
responsive to determining the at least one second DMA transfer, generating data associated with a descriptor based at least on linking the first DMA transfer and the at least one second DMA transfer for the frame; and
providing the data associated with the descriptor to device, the data associated with the descriptor configured to cause the device to obtain the frame data associated with the frame from source memory based at least on the descriptor and store the frame data in destination memory.
20 . The method of claim 19 , wherein determining the at least one second DMA transfer comprises:
determining a sequence of DMA transfers to be performed by the device based at least on the frame, and
wherein generating the data associated with the descriptor comprises:
generating the data associated with the descriptor to cause the device to perform the DMA transfers based at least on an amount of DMA transfers represented by the sequence of DMA transfers.