Systems and methods for high bandwidth memory with unidirectional data flow
The present application relates to systems and methods for providing high bandwidth connections between memory and computing units. For example, memory units can be configured to perform concurrent read and write operations in parallel to one another. The memory units can also be configured to alter the relative bandwidths that are available for the read and write operations. For example, bi-directional transmission interfaces of a memory unit can be assigned to operate as uni-directional interfaces that are a part of either a data input path or a data output path.
1 . A system for computing and memory communication comprising:
a computing unit; and
a high-bandwidth memory (HBM), having a plurality of data transmission interfaces that are bi-directional, wherein the HBM is configured to access assignment data relating to read/write assignments for the plurality of data transmission interfaces and assign a first subset of the data transmission interfaces to operate unidirectionally as a data input path for receiving data corresponding to write operations based on the assignment data, and to assign a second subset of the data transmission interfaces to operate unidirectionally as a data output path for transmitting data corresponding to read operations based on the assignment data, and wherein the HBM is further configured to communicate with the computing unit so as to perform a read operation and a write operation in parallel.
2 . The system of claim 1 , wherein the HBM is configured to assign the first subset of data transmission interfaces and the second subset of the data transmission interfaces based on one or more inputs received from the computing unit.
3 . The system of claim 1 , wherein the assignment data comprises a determined relative ratio between a number of data transmission interfaces in the first subset and a number of data transmission interfaces in the second subset.
4 . The system of claim 1 , wherein the HBM is further configured to re-assign one or more data transmission interfaces of plurality of data transmission interfaces with respect to being in either the first subset or second subset.
5 . The system of claim 4 , wherein re-assigning the one or more data transmission interfaces results in altering a relative ratio of data transmission interfaces that are in the first subset and the second subset.
6 . The system of claim 1 , wherein the HBM is further configured to have a write-address input for receiving transmissions identifying one or more addresses for write operations and a read-address input for receiving transmissions identifying one or more addresses for read operations.
7 . The system of claim 6 , wherein the HBM is further configured to identify a coherency conflict in connection with one or more write operations and one or more read operations.
8 . The system of claim 7 , wherein the HBM is further configured to transmit coherency-related data to the computing unit.
9 . The system of claim 6 , wherein the HBM is further configured to perform the one or more write operations and read operations in a determined order based on identifying the coherency conflict.
10 . A method for computing and memory communication comprising: accessing assignment data relating to read/write assignments for a plurality of data transmission interfaces; assigning, based on the assignment data, a first subset of data transmission interfaces that are bi-directional to operate unidirectionally as a data input path for receiving data corresponding to write operations and a second subset of data transmission interfaces to operate unidirectionally as a data output path for transmitting data corresponding to read operations; receiving, by a high-bandwidth memory (HBM), a first transmission identifying a read operation to be performed and a second transmission identifying a write operation to be performed; and performing, by the HBM, the write operation using the first subset of data transmission interfaces and the read operation using the second subset of data transmission interfaces.
11 . The method of claim 10 , wherein the write operation and the read operation are performed by the HBM in parallel.
12 . The method of claim 10 , wherein the HBM is configured to assign the first subset of data transmission interfaces and the second subset of the data transmission interfaces based on one or more inputs received from the computing unit.
13 . The method of claim 11 , wherein the first subset and second subset are assigned in accordance with a determined relative ratio identified within the assignment data.
14 . The method of claim 10 , further comprising re-assigning one or more data transmission interfaces with respect to being in the first subset or second subset.
15 . The method of claim 14 , wherein re-assigning the one or more data transmission interfaces results in altering a relative ratio of data transmission interfaces that are in the first subset and the second subset.
16 . The method of claim 10 , wherein the HBM receives the first transmission via a read-address input and the second transmission via a write-address input.
17 . The method of claim 16 , further comprising identifying a coherency conflict in connection with one or more write operations and one or more read operations.
18 . The method of claim 17 , further comprising transmitting, by the HBM, coherency-related data to the computing unit.
19 . The method of claim 16 , further comprising performing, by the HBM, the one or more write operations and read operations in a determined order based on the coherency conflict.