Mode switching circuit and method, expansion connector, and PCIe card

1 . A mode switching circuit, comprising: a first switching circuit, a second switching circuit, a clock switching circuit, and a first bidirectional level shifter, wherein

an input terminal of the first switching circuit is configured to be connected to a first reverse differential pin of a connector, a first output terminal of the first switching circuit is configured to be connected to a first reset in-place terminal of a peripheral component interconnect express (PCIe) device, and a second output terminal of the first switching circuit is connected to the clock switching circuit; the first switching circuit is configured to transmit at least one of a root complex (RC) reset signal or an RC in-place signal between the first reverse differential pin and the first reset in-place terminal, or send an endpoint (ED) differential clock signal transmitted by the first reverse differential pin to the clock switching circuit;

a first input terminal of the second switching circuit is configured to be connected to a second reset in-place terminal of the PCIe device, a second input terminal of the second switching circuit is connected to the clock switching circuit, and an output terminal of the second switching circuit is configured to be connected to a first front differential pin of the connector; the second switching circuit is configured to send an RC differential clock signal to the first front differential pin, or at least one of transmit an ED reset signal or an ED in-place signal between the first front differential pin and the second reset in-place terminal;

the clock switching circuit is configured to generate a reference clock signal sent to the PCIe device and the RC differential clock signal sent to the second switching circuit, or generate the reference clock signal sent to the PCIe device according to the ED differential clock signal; and

a first set of level shifting channels of the first bidirectional level shifter is configured to transmit data between a second reverse differential pin of the connector and a first data terminal of the PCIe device, and a second set of level shifting channels of the first bidirectional level shifter is configured to transmit data between a second front differential pin of the connector and a second data terminal of the PCIe device; two sets of level shifting channels of the first bidirectional level shifter are capable of being configured to transmit an inter-integrated circuit (I2C) bus signal or to transmit at least one of a wake-up signal or an identification (ID) signal.

2 . The mode switching circuit according to claim 1 , characterized by further comprising: a first tri-state level shifting circuit, wherein

a first side port of the first tri-state level shifting circuit is connected to the first output terminal of the first switching circuit, and a second side port of the first tri-state level shifting circuit is configured to be connected to the first reset in-place terminal of the PCIe device;

the first tri-state level shifting circuit is configured to: transmit the at least one of the RC reset signal or the RC in-place signal in an RC interface mode; or

a port of the first tri-state level shifting circuit is in a high-impedance state in an ED interface mode.

3 . The mode switching circuit according to claim 2 , wherein the first tri-state level shifting circuit comprises a first tri-state level shifter; the first tri-state level shifter is configured to connect the first output terminal of the first switching circuit and the first reset in-place terminal of the PCIe device; and

an enable terminal of the first tri-state level shifter is configured to be connected to an RC enable signal, and the RC enable signal is valid in the RC interface mode.

4 . The mode switching circuit according to claim 3 , wherein the first tri-state level shifting circuit further comprises: a first level circuit; the first level circuit is connected to a power supply terminal of the first tri-state level shifter;

the first level circuit is configured to: provide a reference level to the first tri-state level shifter in the RC interface mode; or

the first level circuit is configured to: stop supplying power in the ED interface mode.

5 . The mode switching circuit according to claim 4 , wherein the first level circuit comprises: a first switching transistor;

an input terminal of the first switching transistor is connected to a power supply, and an output terminal of the first switching transistor is connected to the power supply terminal of the first tri-state level shifter; and

a control terminal of the first switching transistor is connected to the RC enable signal; and in response to determining that the RC enable signal is valid, the first switching transistor is turned on.

6 . The mode switching circuit according to claim 2 , wherein in the first switching circuit, the input terminal and the second output terminal of the first switching circuit are directly connected through a first wire; and

a pin of the second side port of the first tri-state level shifting circuit is arranged with a first via, and the first wire passes through the first via and is electrically connected with the first via.

7 . The mode switching circuit according to claim 1 , comprising: a second tri-state level shifting circuit, wherein

a first side port of the second tri-state level shifting circuit is connected to the first input terminal of the second switching circuit, and a second side port of the second tri-state level shifting circuit is configured to be connected to the second reset in-place terminal of the PCIe device;

a port of the second tri-state level shifting circuit is in a high-impedance state in an RC interface mode; or

the second tri-state level shifting circuit is configured to: transmit the at least one of the ED reset signal and/or the ED in-place signal in an ED interface mode.

8 . The mode switching circuit according to claim 7 , wherein the second tri-state level shifting circuit comprises a second tri-state level shifter; the second tri-state level shifter is configured to connect the first input terminal of the second switching circuit and the second reset in-place terminal of the PCIe device; and

an enable terminal of the second tri-state level shifter is configured to be connected to an ED enable signal, and the ED enable signal is valid in the ED interface mode.

9 . The mode switching circuit according to claim 8 , wherein the second tri-state level shifting circuit further comprises: a second level circuit; the second level circuit is connected to a power supply terminal of the second tri-state level shifter;

the second level circuit is configured to: stop supplying power in the RC interface mode; or

the second level circuit is configured to: provide a reference level to the second tri-state level shifter in the ED interface mode.

10 . The mode switching circuit according to claim 9 , wherein the second level circuit comprises: a second switching transistor;

an input terminal of the second switching transistor is connected to a power supply, and an output terminal of the second switching transistor is connected to the power supply terminal of the second tri-state level shifter; and

a control terminal of the second switching transistor is connected to the ED enable signal; and in response to determining that the ED enable signal is valid, the second switching transistor is turned on.

11 . The mode switching circuit according to claim 7 , wherein in the second switching circuit, the second input terminal and the output terminal of the second switching circuit are directly connected through a second wire; and

a pin of the first side port of the second tri-state level shifting circuit is arranged with a second via, and the second wire-passes through the second via and is electrically connected with the second via.

12 . The mode switching circuit according to claim 1 , comprising: a second bi-directional level shifter and a third tri-state level shifting circuit, wherein

a first side port of the third tri-state level shifting circuit is connected to a third reverse differential pin of the connector, and a second side port of the third tri-state level shifting circuit is configured to be connected to a third reset in-place terminal of the PCIe device;

a first set of level shifting channels of the second bidirectional level shifter is configured to transmit data between a fourth reverse differential pin of the connector and a third data terminal of the PCIe device, and a second set of level shifting channels of the second bidirectional level shifter is configured to transmit data between a fourth front differential pin of the connector and a fourth data terminal of the PCIe device;

the third tri-state level shifting circuit is configured to transmit the at least one of the RC reset signal and/or the RC in-place signal in an RC interface mode; the first set of level shifting channels of the second bidirectional level shifter is configured to transmit the I2C bus signal, and the second set of level shifting channels of the second bidirectional level shifter is configured to transmit the at least one of the wake-up signal or the ID signal; or

a port of the third tri-state level shifting circuit is in a high-impedance state in an ED interface mode; the first set of level shifting channels of the second bidirectional level shifter is configured to transmit the at least one of the wake-up signal or the ID signal, and the second set of level shifting channels of the second bidirectional level shifter transmits the I2C bus signal.

13 . The mode switching circuit according to claim 1 , wherein the clock switching circuit comprises: a clock generator and a clock buffer;

a first output terminal of the clock generator is connected to a first input terminal of the clock buffer and configured to output a local differential clock signal in an RC interface mode;

a second output terminal of the clock generator is connected to the second input terminal of the second switching circuit and configured to output the RC differential clock signal in the RC interface mode;

a second input terminal of the clock buffer is connected to the second output terminal of the first switching circuit and configured to receive the ED differential clock signal in an ED interface mode; and

the clock buffer is configured to generate the reference clock signal sent to the PCIe device according to the local differential clock signal or the ED differential clock signal.

14 . The mode switching circuit according to claim 13 , wherein an enable terminal of the clock generator is configured to be connected to an RC enable signal; the RC enable signal is valid in the RC interface mode; and

in response to determining that the RC enable signal is valid, the clock generator-outputs the local differential clock signal and the RC differential clock signal.

15 . The mode switching circuit according to claim 13 , wherein a selection terminal of the clock buffer is configured to be connected to a clock selection signal;

in response to determining that the clock selection signal represents the RC interface mode, the first input terminal of the clock buffer is valid; or

in response to determining that the clock selection signal represents the ED interface mode, the second input terminal of the clock buffer is valid.

16 . The mode switching circuit according to claim 1 , further comprising: a mode selection circuit, wherein

the mode selection circuit is configured to provide the PCIe device with a mode selection signal indicating that an RC interface mode is currently selected or an ED interface mode is currently selected.

17 . The mode switching circuit according to claim 16 , wherein the mode selection circuit comprises: a selector switch, a first resistor, and a second resistor;

a first terminal of the first resistor is connected to a power supply, and a second terminal of the first resistor is sequentially connected to ground through the selector switch and the second resistor; or a first terminal of the selector switch is connected to the power supply, and a second terminal of the selector switch is sequentially connected to the ground through the first resistor and the second resistor; and

a terminal of the second resistor close to the first resistor is configured to be connected to the PCIe device to provide the mode selection signal.

18 . A mode switching method, being implemented based on a mode switching circuit,

wherein the mode switching circuit comprises:

a first switching circuit, a second switching circuit, a clock switching circuit, and a first bidirectional level shifter, wherein

an input terminal of the first switching circuit is configured to be connected to a first reverse differential pin of a connector, a first output terminal of the first switching circuit is configured to be connected to a first reset in-place terminal of a peripheral component interconnect express (PCIe) device, and a second output terminal of the first switching circuit is connected to the clock switching circuit; the first switching circuit is configured to transmit at least one of a root complex (RC) reset signal or an RC in-place signal between the first reverse differential pin and the first reset in-place terminal, or send an endpoint (ED) differential clock signal transmitted by the first reverse differential pin to the clock switching circuit;

a first input terminal of the second switching circuit is configured to be connected to a second reset in-place terminal of the PCIe device, a second input terminal of the second switching circuit is connected to the clock switching circuit, and an output terminal of the second switching circuit is configured to be connected to a first front differential pin of the connector; the second switching circuit is configured to send an RC differential clock signal to the first front differential pin, or at least one of transmit an ED reset signal or an ED in-place signal between the first front differential pin and the second reset in-place terminal;

the clock switching circuit is configured to generate a reference clock signal sent to the PCIe device and the RC differential clock signal sent to the second switching circuit, or generate the reference clock signal sent to the PCIe device according to the ED differential clock signal; and

a first set of level shifting channels of the first bidirectional level shifter is configured to transmit data between a second reverse differential pin of the connector and a first data terminal of the PCIe device, and a second set of level shifting channels of the first bidirectional level shifter is configured to transmit data between a second front differential pin of the connector and a second data terminal of the PCIe device; two sets of level shifting channels of the first bidirectional level shifter are capable of being configured to transmit an inter-integrated circuit (I2C) bus signal or to transmit at least one of a wake-up signal or an identification (ID) signal;

wherein the mode switching method comprises:

performing, in an RC interface mode, following steps:

controlling the first switching circuit to transmit the at least one of the RC reset signal or the RC in-place signal between the first reverse differential pin of the connector and the first reset in-place terminal of the PCIe device;

controlling the clock switching circuit to generate the reference clock signal sent to the PCIe device and the RC differential clock signal sent to the second switching circuit; and controlling the second switching circuit to send the RC differential clock signal to the first front differential pin of the connector; and

controlling the first set of level shifting channels of the first bidirectional level shifter to transmit the I2C bus signal, and controlling the second set of level shifting channels of the first bidirectional level shifter to transmit the at least one of the wake-up signal or the ID signal; or

performing, in an ED interface mode, following steps:

controlling the first switching circuit to send the ED differential clock signal transmitted by the first reverse differential pin of the connector to the clock switching circuit;

controlling the clock switching circuit to generate the reference clock signal sent to the PCIe device according to the ED differential clock signal; and controlling the second switching circuit to transmit the at least one of the ED reset signal or the ED in-place signal between the first front differential pin of the connector and the second reset in-place terminal of the PCIe device; and

controlling the first set of level shifting channels of the first bidirectional level shifter to transmit the at least one of the wake-up signal or the ID signal, and controlling the second set of level shifting channels of the first bidirectional level shifter to transmit the I2C bus signal.

19 . A peripheral component interconnect express (PCIe) card, comprising: a PCIe device and at least one expansion connector comprising a connector and a mode switching circuit, wherein the mode switching circuit comprises:

a first switching circuit, a second switching circuit, a clock switching circuit, and a first bidirectional level shifter, wherein

an input terminal of the first switching circuit is configured to be connected to a first reverse differential pin of the connector, a first output terminal of the first switching circuit is configured to be connected to a first reset in-place terminal of a peripheral component interconnect express (PCIe) device, and a second output terminal of the first switching circuit is connected to the clock switching circuit; the first switching circuit is configured to transmit at least one of a root complex (RC) reset signal or an RC in-place signal between the first reverse differential pin and the first reset in-place terminal, or send an endpoint (ED) differential clock signal transmitted by the first reverse differential pin to the clock switching circuit;

a first input terminal of the second switching circuit is configured to be connected to a second reset in-place terminal of the PCIe device, a second input terminal of the second switching circuit is connected to the clock switching circuit, and an output terminal of the second switching circuit is configured to be connected to a first front differential pin of the connector; the second switching circuit is configured to send an RC differential clock signal to the first front differential pin, or at least one of transmit an ED reset signal or an ED in-place signal between the first front differential pin and the second reset in-place terminal;

the clock switching circuit is configured to generate a reference clock signal sent to the PCIe device and the RC differential clock signal sent to the second switching circuit, or generate the reference clock signal sent to the PCIe device according to the ED differential clock signal; and

a first set of level shifting channels of the first bidirectional level shifter is configured to transmit data between a second reverse differential pin of the connector and a first data terminal of the PCIe device, and a second set of level shifting channels of the first bidirectional level shifter is configured to transmit data between a second front differential pin of the connector and a second data terminal of the PCIe device; two sets of level shifting channels of the first bidirectional level shifter are capable of being configured to transmit an inter-integrated circuit (I2C) bus signal or to transmit at least one of a wake-up signal or an identification (ID) signal;

wherein the PCIe device is provided with RC firmware and ED firmware;

the PCIe device loads the RC firmware in an RC interface mode; or

the PCIe device loads the ED firmware in an ED interface mode.

20 . The PCIe card according to claim 19 , wherein the at least one expansion connector comprises a mode selection circuit, and the PCIe device is configured to:

load the RC firmware in response to an RC mode instruction triggered based on the mode selection circuit; or

load the ED firmware in response to an ED mode instruction triggered based on the mode selection circuit.