Memory device for performing target refresh operation, and operation method thereof
A memory device includes a refresh latch configured to generate a first aggressive address by latching an address input with a refresh management command; a detection circuit configured to sequentially store the first aggressive address as a plurality of first candidate addresses, and generate a detection signal according to a number of duplicated addresses among the plurality of the first candidate addresses; an address sampling circuit configured to generate a second aggressive address by collecting information on rows subjected to a row-hammer attack; and an output control circuit configured to output, as a target address, the first aggressive address or the second aggressive address according to the refresh management command and the detection signal.
1 . A memory device, comprising:
a refresh latch configured to generate a first aggressive address by latching an address input with a refresh management command, wherein the address input with the refresh management command includes first information on row-hammer-attacked rows having been subjected to a row-hammer attack, the first information collected by a memory controller based on at least one method of counting an activation number of the row-hammer-attacked rows and randomly sampling rows activated in the memory device;
a detection circuit configured to:
determine, according to refresh rate information, whether to activate an additional refresh signal when the refresh management command is input, and
generate a detection signal when the refresh management command is input and the additional refresh signal is determined to be deactivated;
an address sampling circuit configured to generate a second aggressive address by collecting second information on the row-hammer-attacked rows having been subjected to the row-hammer attack based on the activation number of the row-hammer-attacked rows;
a row control circuit configured to refresh, according to the refresh management command, one or more first adjacent rows of a first target row corresponding to the first aggressive address; and
the row control circuit configured to refresh, according to the refresh management command, one or more adjacent rows of a second target row corresponding to the second aggressive address when it is determined that refreshing for second adjacent rows of the first target row is omitted according to refresh rate information; and
an output control circuit configured to output, as a target address, the first aggressive address or the second aggressive address according to the refresh management command and the detection signal.
2 . The memory device of claim 1 , further comprising: an adjacent address calculating circuit configured to calculate, using the target address, one or more row-hammer addresses according to the additional refresh signal.
3 . The memory device of claim 2 , wherein the adjacent address calculating circuit is configured to:
calculate the row-hammer addresses by increasing and/or decreasing the target address by one (1) when the additional refresh signal is deactivated; and
calculate the row-hammer addresses by increasing and/or decreasing the target address by two (2) when the additional refresh signal is activated.
4 . The memory device of claim 1 , wherein the output control circuit is configured to output as the target address:
the first aggressive address in response to the refresh management command, and
the second aggressive address in response to the detection signal.