IP Library Granted Patent US 12705403
Granted Patent B2
US 12705403 · App. 18/622,738 · Granted Aug 11, 2026

Devices and systems for enforcing confidential computing

Inventors: Nippon Raval (Markham, CA); Alexander J. Branover (Boxborough, MA); Philip Ng (Markham, CA); Donald Matthews, Jr. (Ft. Collins, CO); Anthony Asaro (Markham, CA)
Assignees: Advanced Micro Devices, Inc.; ATI Technologies ULC
G06F21/78G06F21/6218
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12705403
App. No.
18/622,738
Granted
Aug 11, 2026
Kind
B2
Abstract

The disclosed device includes a device comprising a device-attached memory and a trust controller for confidential computing. The trust controller can maintain a record of devices that are permitted to access the device-attached memory, receive updates to the record, and verify, based on the record, attempts to access the memory.

Claims (43)

1 . A device comprising:

a device-attached memory; and

a trust controller that is configured to:

maintain a record of identifiers corresponding to valid requests to access the device-attached memory; and

verify, based on the record, attempts to access the device-attached memory, wherein verifying the attempts to access the device-attached memory comprises examining a source of a memory request and a guest identifier included in the memory request.

2 . The device of claim 1 , wherein updates to the record of the trust controller are issued from a host system that is communicatively coupled to the device.

3 . The device of claim 2 , wherein the host system comprises a memory management unit that initiates the updates to the record of the trust controller.

4 . The device of claim 3 , wherein a memory request bypasses the memory management unit of the host system.

5 . The device of claim 2 , wherein a memory request by the host system to access a host-owned memory of the device-attached memory bypasses the trust controller of the device.

6 . The device of claim 2 , wherein a memory request by the device to access a host-owned memory is routed through a trust controller of the host system.

7 . The device of claim 2 , wherein a memory request by the host system to access a host-owned memory is routed through the trust controller of the device.

8 . The device of claim 2 , wherein a memory request by the device to access the device-attached memory is routed through the trust controller of the device.

9 . The device of claim 2 , wherein:

the device issues a request to access a host-owned block of the device-attached memory;

the host system updates ownership of the host-owned block of the device-attached memory, thereby changing the host-owned block of the device-attached memory to a device-owned portion of the device-attached memory; and

the device routes the request to the device-owned portion of the device-attached memory.

10 . The device of claim 2 , wherein updates to the record are broadcasted to each device connected to the host system.

11 . The device of claim 1 , wherein the device requests to access an additional device-attached memory communicatively coupled to an additional device.

12 . The device of claim 1 , wherein the trust controller of the device is configured to:

receive updates to the record; and

verify, based on the updated record, an identifier corresponding to a memory request.

13 . The device of claim 1 , wherein examining the source of the memory request comprises examining an identifier of the source of the memory request, and the guest identifier includes or is based on an identifier of an address space.

14 . The device of claim 1 , wherein:

an update to the record specifies a change in ownership of a block of memory of the device-attached memory; and

the device-attached memory sanitizes the block of memory in response to receiving the update.

15 . The device of claim 14 , further comprises flushing a local cache of the device in response to receiving the update.

16 . A system comprising:

a host device, the host device comprising:

a host memory;

a host trust controller that is configured to:

maintain a record of identifiers corresponding to valid requests to access the host memory;

receive updates to the record; and

verify, based on the record, attempts to access the host memory, wherein verifying the attempts to access the host memory comprises examining a source of a memory request and a value included in the memory request, wherein the value includes or is based on an identifier of an address space; and

an additional device that stores data in the host memory.

17 . The system of claim 16 , wherein a memory request directed to a local cache of the host device is routed to the additional device in response to a cache miss at the host device.

18 . The system of claim 16 , wherein the host trust controller is configured to:

verify, based on an update to the record, whether the additional device is permitted to access the host memory.

19 . The system of claim 16 , wherein updates to the record are broadcasted to each device connected to the host device.

20 . A method comprising:

updating an entry in a local registry of a trust controller of a device, the entry corresponding to a memory block of a physical memory of the device and further including identifiers corresponding to valid requests to access the memory block;

receiving a request to access the memory block;

verifying, based on comparing information in the request to information recorded in the local registry, that the request is a valid request to access the memory block, wherein the verifying comprises examining a source of a memory request and a value included in the memory request, wherein the value includes or is based on an identifier of an address space; and

granting, based on verifying the information in the request, access to the memory block.