Scalable control of quantum bits using baseband pulsing
According to one aspect of the disclosure, a system for performing quantum computations includes: a first environment for being maintained at an ambient temperature, having a classical computing processor; and a second environment for being maintained at a cryogenic temperature, having a plurality of qubits and a multiplexing circuit coupled to the plurality of qubits, each of the plurality of qubits having a gap transition frequency; wherein the classical computing processor is configured to change the states of each of the plurality of qubits by controlling the multiplexing circuit to couple particular ones of the plurality of qubits to a pulsed baseband waveform.
1 . A system for performing quantum computations, the system comprising:
a first environment for being maintained at an ambient temperature, having a classical computing processor; and
a second environment for being maintained at a cryogenic temperature, having a plurality of qubits and a multiplexing circuit coupled to the plurality of qubits, each of the plurality of qubits having a respective gap transition frequency,
wherein the classical computing processor is configured to change a state of particular ones of the of the plurality of qubits by controlling the multiplexing circuit to couple the particular ones of the plurality of qubits to a pulsed baseband waveform,
wherein the pulsed baseband waveform comprises a non-adiabatic waveform that is not resonant with respect to the respective gap transition frequencies of the particular ones of the plurality of qubits.
2 . The system of claim 1 , wherein the multiplexing circuit comprises a plurality of switches arranged in a binary tree structure.
3 . The system of claim 1 , wherein the pulsed baseband waveform comprises a first pulse having a first duration and a positive amplitude, and a second pulse having a second duration and a negative amplitude.
4 . The system of claim 3 , wherein the first pulse, the second pulse, or both are square pulses.
5 . The system of claim 1 , further comprising a driver circuit to generate the pulsed baseband waveform.
6 . The system of claim 5 , wherein the driver circuit is located within the first environment for being maintained at the ambient temperature.
7 . The system of claim 5 , wherein the driver circuit is located within the second environment for being maintained at the cryogenic temperature.
8 . The system of claim 7 , wherein the driver circuit is implemented using cryogenic CMOS or single-flux quantum (SFQ) logic.
9 . The system of claim 1 , wherein the multiplexer circuit is located within the second environment for being maintained at the cryogenic temperature.
10 . The system of claim 9 , wherein the multiplexer circuit is implemented using cryogenic CMOS or single-flux quantum (SFQ) logic.
11 . The system of claim 9 , wherein the multiplexer circuit is collocated on a same chip as one or more of the plurality of qubits.
12 . The system of claim 1 , wherein the multiplexer circuit is bump bonded or wafer bonded to the plurality of qubits.
13 . The system of claim 1 , wherein the multiplexer circuit is connected to each of the plurality of qubits via chip-level interconnects.
14 . A quantum computing system comprising:
a classical computing processor;
a quantum processing unit (QPU) having a plurality of qubits with respective gap transition frequencies; and
a multiplexer configured to couple particular ones of the plurality of qubits to a pulsed baseband waveform responsive to commands received from the classical computing processor,
wherein the pulsed baseband waveform comprises a non-adiabatic waveform that is not resonant with respect to the respective gap transition frequencies of the particular ones of the plurality of qubits.
15 . The quantum computing system of claim 14 , wherein the pulsed baseband waveform comprises a first pulse having a first duration and a positive amplitude, and a second pulse having a second duration and a negative amplitude.
16 . The quantum computing system of claim 15 , wherein the first pulse, the second pulse, or both are square pulses.
17 . The quantum computing system of claim 14 , wherein the classical computing processor is maintained at an ambient temperature, and both the QPU and the multiplexer are maintained at a cryogenic temperature.
18 . The quantum computing system of claim 14 , further comprising a driver to generate the pulsed baseband waveform.
19 . The quantum computing system of claim 14 , wherein the multiplexer is collocated on a same chip as one or more of the plurality of qubits.