Display device
A display device includes a gate driver which supplies a gate signal to pixels and includes a plurality of stages, wherein each of the stages includes a pull-down unit which outputs a first voltage applied to a first voltage line responsive to a voltage of a Q node as the gate signal, a pull-up unit which outputs a second voltage applied to a second voltage line responsive to a voltage of a QB node as the gate signal, a Q node controller which controls the voltage of the Q node responsive to a start signal and a clock signal and a QB node controller which includes a first transistor including a gate electrode connected to a clock signal line to which the clock signal is supplied and controls the voltage of the QB node responsive to the clock signal, the start signal, and the voltage of the Q node.
1 . A display device, comprising:
a display panel including a plurality of pixels; and
a gate driver configured to supply a gate signal to the plurality of pixels, the gate driver including a plurality of stages that each comprise:
a pull-down circuit configured to output as the gate signal a first voltage that is applied to a first voltage line responsive to a voltage of a Q node;
a pull-up circuit configured to output as the gate signal a second voltage that is applied to a second voltage line responsive to a voltage of a QB node;
a Q node controller connected to the Q node, the Q node controller configured to control the voltage of the Q node responsive to a start signal and a clock signal received by the Q node controller; and
a QB node controller connected to the QB node, the QB node controller including a first transistor having a gate electrode that is connected to a clock signal line that supplies the clock signal and controls the voltage of the QB node responsive to the clock signal, the start signal, and the voltage of the Q node,
wherein the QB node controller further includes a third transistor including a gate electrode connected to a drain electrode of the first transistor at a QP node, a source electrode connected to the first voltage line, and a drain electrode connected to the QB node.
2 . The display device according to claim 1 ,
wherein the first transistor further includes a source electrode connected to the clock signal line;
wherein the QB node controller further includes:
a second transistor including a gate electrode connected to a start signal line that supplies the start signal, a source electrode connected to the second voltage line, and a drain electrode connected to the drain electrode of the first transistor at the QP node; and
a fourth transistor including a gate electrode connected to the Q node, a source electrode connected to the second voltage line, and a drain electrode connected to the drain electrode of the third transistor at the QB node.
3 . The display device according to claim 1 ,
wherein the first transistor further includes a source electrode connected to an inverted start signal line that supplies an inverted start signal that is inverted with respect to the start signal or a line connected to a QB node of a previous stage from the plurality of stages;
wherein the QB node controller further includes:
a second transistor including a gate electrode connected to a start signal line that supplies the start signal, a source electrode connected to the second voltage line, and a drain electrode connected to the drain electrode of the first transistor at the QP node; and
a fourth transistor including a gate electrode connected to the Q node, a source electrode connected to the first voltage line, and a drain electrode connected to the drain electrode of the third transistor at the QB node.
4 . The display device according to claim 1 ,
wherein the first transistor further includes a source electrode electrically connected to the first voltage line;
wherein the QB node controller further includes:
a second transistor including a gate electrode connected to a start signal line that supplies the start signal, a source electrode connected to the second voltage line, and a drain electrode connected to the drain electrode of the first transistor at the QP node; and
a fourth transistor including a gate electrode connected to the Q node, a source electrode connected to the second voltage line, and a drain electrode connected to the QB node.
5 . The display device according to claim 4 , wherein the QB node controller further includes:
a ninth transistor including a gate electrode connected to an inverted start signal line that supplies an inverted start signal that is inverted with respect to the start signal or a line connected to a QB node of a previous stage from the plurality of stages, a source electrode connected to the first voltage line, and a drain electrode connected to the source electrode of the first transistor,
wherein the ninth transistor is configured to electrically connect the first transistor to the first voltage line.
6 . The display device according to claim 1 , wherein the display panel includes an active area in which the plurality of pixels are disposed and a non-active area that encloses the active area,
wherein the gate driver is in the active area.
7 . The display device according to claim 6 , wherein the display device further comprises:
a gate link line supplying one or more of the start signal, the clock signal, the first voltage, and the second voltage,
wherein the gate link line comprises a second gate link line in the active area.
8 . The display device according to claim 7 , wherein two second gate link lines are at an edge of the active area adjacent to the non-active area, and extend in a row direction of the active area on two sides of a flexible film respectively.
9 . The display device according to claim 8 , wherein the gate link line further comprises first gate link lines and third gate link lines,
wherein the first gate link lines are connected to the two sides of the flexible film respectively, the two second gate link lines are connected to the first gate link lines respectively, and the third gate link lines are connected to the two second gate link lines respectively and extend in a column direction crossing the row direction of the active area.
10 . The display device according to claim 1 , wherein the Q node controller includes:
a fifth transistor including a source electrode connected to a start signal line to which the start signal is supplied, a drain electrode connected to the Q node, and a gate electrode connected to the clock signal line.
11 . The display device according to claim 10 , wherein the Q node includes a Q 1 node and a Q 2 node and the display device further comprises:
a stabilizer circuit connected to the Q 1 node and the Q 2 node.
12 . The display device according to claim 11 , wherein the stabilizer circuit comprises:
a sixth transistor including a source electrode connected to the drain electrode of the fifth transistor at the Q 1 node, a drain electrode connected to the Q 2 node, and a gate electrode connected to the first voltage line.
13 . The display device according to claim 12 , wherein the pull-down circuit includes:
a seventh transistor including a gate electrode connected to the drain electrode of the sixth transistor at the Q 2 node, a source electrode connected to the first voltage line, and a drain electrode connected to an output terminal that outputs the gate signal; and
a second capacitor connected to the Q 2 node and the output terminal, and
wherein the pull-up circuit includes an eighth transistor including a gate electrode connected to the QB node, a source electrode connected to the output terminal, and a drain electrode connected to the second voltage line.
14 . The display device according to claim 1 , wherein the first voltage is a gate low voltage and the second voltage is a gate high voltage that is greater than the gate low voltage.
15 . The display device according to claim 1 , wherein the QB node controller further includes a first capacitor connected to the QB node and the second voltage line.