Display device and electronic device including the same

1 . A display device comprising:

a first sub-pixel comprising a first sub-pixel circuit, and a first light-emitting element configured to emit light based on a first data signal;

a second sub-pixel comprising a second sub-pixel circuit, and a second light-emitting element configured to emit light based on a second data signal; and

a third sub-pixel comprising a third sub-pixel circuit, and a third light-emitting element configured to emit light based on a third data signal,

wherein channels of transistors configured to perform a same function among transistors in the first, second, and third sub-pixel circuits are adjacent to each other,

wherein a channel of a (1_1)th transistor of the first sub-pixel, a channel of a (1_2)th transistor of the second sub-pixel, and a channel of a (1_3)th transistor of the third sub-pixel extend in a first direction, and

wherein the channel of the (1_1)th transistor of the first sub-pixel, the channel of the (1_2)th transistor of the second sub-pixel, and the channel of the (1_3)th transistor of the third sub-pixel are spaced apart from each other in a second direction perpendicular to the first direction.

2 . The display device of claim 1 , wherein the first sub-pixel circuit comprises the (1_1)th transistor configured to generate a driving current based on the first data signal, and a (2_1)th transistor configured to provide the first data signal to the (1_1)th transistor in response to a first gate signal provided to a first sub-gate line,

wherein the second sub-pixel circuit comprises the (1_2)th transistor configured to generate a driving current based on the second data signal, and a (2_2)th transistor configured to provide the second data signal to the (1_2)th transistor in response to the first gate signal,

wherein the third sub-pixel circuit comprises the (1_3)th transistor configured to generate a driving current based on the third data signal, and a (2_3)th transistor configured to provide the third data signal to the (1_3)th transistor in response to the first gate signal,

wherein the channel of the (1_1)th transistor, the channel of the (1_2)th transistor, and the channel of the (1_3)th transistor are adjacent to each other, and

wherein a channel of the (2_1)th transistor, a channel of the (2_2)th transistor, and a channel of the (2_3)th transistor are adjacent to each other.

3 . The display device of claim 2 , wherein a distance between the channel of the (1_1)th transistor and the channel of the (2_1)th transistor is greater than a distance between the channel of the (1_1)th transistor and the channel of the (1_2)th transistor in plan view.

4 . The display device of claim 2 , wherein the channel of the (1_1)th transistor, the channel of the (1_2)th transistor, and the channel of the (1_3)th transistor are in a first channel area, and

wherein the channel of the (2_1)th transistor, the channel of the (2_2)th transistor, and the channel of the (2_3)th transistor are in a second channel area.

5 . The display device of claim 4 , wherein a (1_1)th gate electrode, a (1_2)th gate electrode, and a (1_3)th gate electrode are in the first channel area, and

wherein one gate electrode is in a channel area comprising a transistor that is other than transistors configured to generate a driving current.

6 . The display device of claim 5 , wherein one second gate electrode is in the second channel area.

7 . The display device of claim 6 , wherein the second gate electrode overlaps the channel of the (2_1)th transistor, the channel of the (2_2)th transistor, and the channel of the (2_3)th transistor in plan view.

8 . The display device of claim 5 , wherein some of channels in a pixel are arranged along the first direction, and others of the channels in the pixel are arranged along the second direction.

9 . A display device comprising:

a first sub-pixel comprising a first sub-pixel circuit, and a first light-emitting element configured to emit light based on a first data signal;

a second sub-pixel comprising a second sub-pixel circuit, and a second light-emitting element configured to emit light based on a second data signal; and

a third sub-pixel comprising a third sub-pixel circuit, and a third light-emitting element configured to emit light based on a third data signal,

wherein channels of transistors configured to perform a same function among transistors in the first, second, and third sub-pixel circuits are adjacent to each other,

wherein the first sub-pixel circuit comprises a (1_1)th transistor configured to generate a driving current based on the first data signal, and a (2_1)th transistor configured to provide the first data signal to the (1_1)th transistor in response to a first gate signal provided to a first sub-gate line,

wherein the second sub-pixel circuit comprises a (1_2)th transistor configured to generate a driving current based on the second data signal, and a (2_2)th transistor configured to provide the second data signal to the (1_2)th transistor in response to the first gate signal,

wherein the third sub-pixel circuit comprises a (1_3)th transistor configured to generate a driving current based on the third data signal, and a (2_3)th transistor configured to provide the third data signal to the (1_3)th transistor in response to the first gate signal,

wherein a channel of the (1_1)th transistor, a channel of the (1_2)th transistor, and a channel of the (1_3)th transistor are adjacent to each other,

wherein a channel of the (2_1)th transistor, a channel of the (2_2)th transistor, and a channel of the (2_3)th transistor are adjacent to each other,

wherein the channel of the (1_1)th transistor, the channel of the (1_2)th transistor, and the channel of the (1_3)th transistor are in a first channel area,

wherein the channel of the (2_1)th transistor, the channel of the (2_2)th transistor, and the channel of the (2_3)th transistor are in a second channel area

wherein a (1_1)th gate electrode, a (1_2)th gate electrode, and a (1_3)th gate electrode are in the first channel area,

wherein one gate electrode is in a channel area comprising a transistor that is other than transistors configured to generate a driving current,

wherein some of channels in a pixel are arranged along a first direction, and others of the channels in the pixel are arranged along a second direction perpendicular to the first direction,

wherein the (1_1)th transistor is connected between a power node configured to provide a power voltage and a (1_1)th node,

wherein the (1_2)th transistor is connected between the power node and a (1_2)th node,

wherein the (1_3)th transistor is connected between the power node and a (1_3)th node,

wherein the first sub-pixel circuit further comprises a (3_1)th transistor connected between the (1_1)th gate electrode of the (1_1)th transistor and the (1_1)th node, the (3_1)th transistor configured to operate in response to a second gate signal provided to a second sub-gate line,

wherein the second sub-pixel circuit further comprises a (3_2)th transistor connected between the (1_2)th gate electrode of the (1_2)th transistor and the (1_2)th node, the (3_2)th transistor configured to operate in response to the second gate signal, and

wherein the third sub-pixel circuit further comprises a (3_3)th transistor connected between the (1_3)th gate electrode of the (1_3)th transistor and the (1_3)th node, the (3_3)th transistor configured to operate in response to the second gate signal.

10 . The display device of claim 9 , wherein a channel of the (3_1)th transistor is not between the channel of the (1_1)th transistor and the channel of the (1_2)th transistor.

11 . The display device of claim 9 , wherein a channel of the (3_1)th transistor, a channel of the (3_2)th transistor, and a channel of the (3_3)th transistor are in a third channel area,

wherein the channels in the third channel area are arranged along the first direction, and

wherein the channels in the first channel area are arranged along the second direction.

12 . The display device of claim 11 , wherein one third gate electrode is in the third channel area.

13 . The display device of claim 12 , wherein the third gate electrode overlaps the channel of the (3_1)th transistor, the channel of the (3_2)th transistor, and the channel of the (3_3)th transistor in plan view.

14 . The display device of claim 13 , wherein the first sub-pixel circuit further comprises a (4_1)th transistor connected between the (1_1)th node and an anode electrode of the first light-emitting element, the (4_1)th transistor configured to operate in response to a third gate signal provided to a sub-emission control line,

wherein the second sub-pixel circuit further comprises a (4_2)th transistor connected between the (1_2)th node and an anode electrode of the second light-emitting element, the (4_2)th transistor configured to operate in response to the third gate signal, and

wherein the third sub-pixel circuit further comprises a (4_3)th transistor connected between the (1_3)th node and an anode electrode of the third light-emitting element, the (4_3)th transistor configured to operate in response to the third gate signal.

15 . The display device of claim 14 , wherein a channel of the (4_1)th transistor, a channel of the (4_2)th transistor, and a channel of the (4_3)th transistor are in a fourth channel area, and

wherein the third channel area contacts the fourth channel area.

16 . The display device of claim 15 , wherein one fourth gate electrode is in the fourth channel area, and

wherein the fourth gate electrode overlaps the channel of the (4_1)th transistor, the channel of the (4_2)th transistor, and the channel of the (4_3)th transistor in plan view.

17 . The display device of claim 16 , further comprising:

a third electrode layer constituting the first and second sub-gate lines and the sub-emission control line;

a fourth electrode layer constituting a first data line configured to provide the first data signal, a second data line configured to provide the second data signal, and a third data line configured to provide the third data signal; and

via holes through which the fourth electrode layer is connected to the third electrode layer.

18 . The display device of claim 17 , wherein one of the via holes connected to the anode electrode of the second light-emitting element and the (4_1)th transistor overlap in plan view.

19 . The display device of claim 18 , wherein the first sub-pixel circuit further comprises a (5_1)th transistor connected between the anode electrode of the first light-emitting element and an initialization voltage node configured to receive an initialization voltage,

wherein the second sub-pixel circuit further comprises a (5_2)th transistor connected between the anode electrode of the second light-emitting element and the initialization voltage node, and

wherein the third sub-pixel circuit further comprises a (5_3)th transistor connected between the anode electrode of the third light-emitting element and the initialization voltage node.

20 . The display device of claim 19 , wherein a channel of the (5_1)th transistor, a channel of the (5_2)th transistor, and a channel of the (5_3)th transistor are in a fifth channel area, and

wherein a distance between the third channel area and the fifth channel area is greater than a distance between the third channel area and the first channel area.

21 . An electronic device comprising a display device comprising:

a first sub-pixel comprising a first sub-pixel circuit, and a first light-emitting element configured to emit light based on a first data signal;

a second sub-pixel comprising a second sub-pixel circuit, and a second light-emitting element configured to emit light based on a second data signal; and

a third sub-pixel comprising a third sub-pixel circuit, and a third light-emitting element configured to emit light based on a third data signal,

wherein channels of transistors configured to perform a same function among transistors in the first, second, and third sub-pixel circuits are adjacent to each other,

wherein a channel of a (1_1)th transistor of the first sub-pixel, a channel of a (1_2)th transistor of the second sub-pixel, and a channel of a (1_3)th transistor of the third sub-pixel extend in a first direction, and

wherein the channel of the (1_1)th transistor of the first sub-pixel, the channel of the (1_2)th transistor of the second sub-pixel, and the channel of the (1_3)th transistor of the third sub-pixel are spaced apart from each other in a second direction perpendicular to the first direction.

22 . The electronic device of claim 21 , wherein the electronic device comprises a smartphone, a television, a monitor, a tablet, an electric vehicle, a mobile phone, a tablet personal computer (PC), a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, an ultra-mobile PC (UMPC), a laptop computer, a billboard, an Internet of Things (IoT) device, a smartwatch, a watch phone, or a head-mounted display (HMD).