IP Library › Granted Patent US 12706030
Granted Patent B2
US 12706030 · App. 19/219,174 · Granted Aug 11, 2026

Gate driving circuit, display device including the gate driving circuit and electronic device including the gate driving circuit

Inventors: Wonjun Lee (Yongin-si, KR); Sungmin Son (Yongin-si, KR); Chaehan Hyun (Yongin-si, KR); Minji Kim (Yongin-si, KR); Geumju Moon (Yongin-si, KR); Hyungjin Song (Yongin-si, KR); Soojo Ock (Yongin-si, KR)
Assignee: SAMSUNG DISPLAY CO., LTD.
G09G3/32G09G2310/0267G09G2310/0286G09G2310/08G09G2320/0233
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Quick Facts
Patent No.
US 12706030
App. No.
19/219,174
Granted
Aug 11, 2026
Kind
B2
Abstract

A gate driving circuit includes a first control circuit for controlling a voltage of a first control node, a second control circuit for controlling a voltage of a second control node, and an output circuit for outputting a first clock signal or a first voltage as a gate signal based on the voltage of the first control node and the voltage of the second control node. The second control circuit includes a switching circuit connected to a first node and a second node, and for receiving the second clock signal, a second capacitor including a first electrode connected to the first node and a second electrode connected to the second node, and a fourth capacitor including a first electrode for receiving a second voltage and a second electrode connected to the second node.

Claims (98)

1 . A gate driving circuit comprising:

a first control circuit configured to control a voltage of a first control node based on an input signal, a first clock signal and a second clock signal;

a second control circuit configured to control a voltage of a second control node based on the first clock signal and the second clock signal; and

an output circuit configured to output the first clock signal or a first voltage as a gate signal based on the voltage of the first control node and the voltage of the second control node,

wherein the second control circuit includes:

a switching circuit connected to a first node and a second node, and configured to receive the second clock signal;

a second capacitor including a first electrode connected to the first node and a second electrode connected to the second node; and

a fourth capacitor including a first electrode configured to receive a second voltage and a second electrode connected to the second node.

2 . The gate driving circuit of claim 1 , wherein the switching circuit includes:

a sixth transistor including a control electrode connected to the first node, a first electrode connected to a third node and a second electrode configured to receive the second clock signal; and

a seventh transistor including a control electrode connected to the first node, a first electrode connected to the second node and a second electrode connected to the third node.

3 . The gate driving circuit of claim 1 , wherein the switching circuit includes a seventh transistor including a control electrode connected to the first node, a first electrode connected to the second node and a second electrode configured to receive the second clock signal.

4 . The gate driving circuit of claim 1 , wherein the second voltage is substantially the same as the first voltage.

5 . The gate driving circuit of claim 1 , wherein the second control circuit further includes:

a third transistor including a control electrode configured to receive the first clock signal, a first electrode configured to receive the first voltage and a second electrode connected to a fifth node;

a fourth transistor including a control electrode configured to receive the first voltage, a first electrode connected to the fifth node and a second electrode connected to the first node;

a fifth transistor including a control electrode connected to the first control node, a first electrode configured to receive the first clock signal and a second electrode connected to the fifth node;

an eighth transistor including a control electrode configured to receive the second clock signal, a first electrode connected to the second node and a second electrode connected to the second control node; and

a first capacitor including a first electrode configured to receive the first clock signal and a second electrode connected to the second control node.

6 . The gate driving circuit of claim 1 , wherein the first control circuit includes:

a first transistor including a control electrode configured to receive the first clock signal, a first electrode configured to receive the input signal and a second electrode connected to a fourth node;

a second transistor including a control electrode connected to the first control node, a first electrode connected to a sixth node and a second electrode configured to receive the second clock signal;

an eleventh transistor including a control electrode configured to receive the first voltage, a first electrode connected to the fourth node and a second electrode connected to the first control node; and

a third capacitor including a first electrode connected to the first control node and a second electrode connected to the sixth node.

7 . The gate driving circuit of claim 1 , wherein the output circuit includes:

a ninth transistor including a control electrode connected to the second control node, a first electrode configured to receive the first clock signal and a second electrode connected to an output node; and

a tenth transistor including a control electrode connected to the first control node, a first electrode connected to the output node and a second electrode configured to receive the first voltage.

8 . The gate driving circuit of claim 1 , further including a reset circuit configured to initialize the first control node and the second control node based on a reset signal,

wherein the reset circuit includes:

a twelfth transistor including a control electrode configured to receive the reset signal, a first electrode configured to receive the first clock signal and a second electrode connected to a fourth node; and

a thirteenth transistor including a control electrode configured to receive the reset signal, a first electrode connected to the second control node and a second electrode configured to receive the first voltage.

9 . A display device comprising:

a display panel including a plurality of pixels;

a data driving circuit configured to provide a data voltage to the pixels;

a gate driving circuit configured to provide a gate signal to the pixels; and

a driving controller configured to control the data driving circuit and the gate driving circuit,

wherein the gate driving circuit includes:

a first control circuit configured to control a voltage of a first control node based on an input signal, a first clock signal and a second clock signal;

a second control circuit configured to control a voltage of a second control node based on the first clock signal and the second clock signal; and

an output circuit configured to output the first clock signal or a first voltage as the gate signal based on the voltage of the first control node and the voltage of the second control node,

wherein the second control circuit includes:

a switching circuit connected to a first node and a second node, and configured to receive the second clock signal;

a second capacitor including a first electrode connected to the first node and a second electrode connected to the second node; and

a fourth capacitor including a first electrode configured to receive a second voltage and a second electrode connected to the second node.

10 . The display device of claim 9 , wherein the switching circuit includes:

a sixth transistor including a control electrode connected to the first node, a first electrode connected to a third node and a second electrode configured to receive the second clock signal; and

a seventh transistor including a control electrode connected to the first node, a first electrode connected to the second node and a second electrode connected to the third node.

11 . The display device of claim 9 , wherein the switching circuit includes a seventh transistor including a control electrode connected to the first node, a first electrode connected to the second node and a second electrode configured to receive the second clock signal.

12 . The display device of claim 9 , wherein the second voltage is substantially the same as the first voltage.

13 . The display device of claim 9 , wherein the second control circuit further includes:

a third transistor including a control electrode configured to receive the first clock signal, a first electrode configured to receive the first voltage and a second electrode connected to a fifth node;

a fourth transistor including a control electrode configured to receive the first voltage, a first electrode connected to the fifth node and a second electrode connected to the first node;

a fifth transistor including a control electrode connected to the first control node, a first electrode configured to receive the first clock signal and a second electrode connected to the fifth node;

an eighth transistor including a control electrode configured to receive the second clock signal, a first electrode connected to the second node and a second electrode connected to the second control node; and

a first capacitor including a first electrode configured to receive the first clock signal and a second electrode connected to the second control node.

14 . The display device of claim 9 , wherein the first control circuit includes:

a first transistor including a control electrode configured to receive the first clock signal, a first electrode configured to receive the input signal and a second electrode connected to a fourth node;

a second transistor including a control electrode connected to the first control node, a first electrode connected to a sixth node and a second electrode configured to receive the second clock signal;

an eleventh transistor including a control electrode configured to receive the first voltage, a first electrode connected to the fourth node and a second electrode connected to the first control node; and

a third capacitor including a first electrode connected to the first control node and a second electrode connected to the sixth node.

15 . The display device of claim 9 , wherein the output circuit includes:

a ninth transistor including a control electrode connected to the second control node, a first electrode configured to receive the first clock signal and a second electrode connected to an output node; and

a tenth transistor including a control electrode connected to the first control node, a first electrode connected to the output node and a second electrode configured to receive the first voltage.

16 . The display device of claim 9 , wherein the gate driving circuit further includes a reset circuit configured to initialize the first control node and the second control node based on a reset signal,

wherein the reset circuit includes:

a twelfth transistor including a control electrode configured to receive the reset signal, a first electrode configured to receive the first clock signal and a second electrode connected to a fourth node; and

a thirteenth transistor including a control electrode configured to receive the reset signal, a first electrode connected to the second control node and a second electrode configured to receive the first voltage.

17 . An electronic device comprising:

a display panel including a plurality of pixels;

a data driving circuit configured to provide a data voltage to the pixels;

a gate driving circuit configured to provide a gate signal to the pixels;

a driving controller configured to control the data driving circuit and the gate driving circuit; and

a processor configured to output a power-on signal, input image data and an input control signal to the driving controller,

wherein when the electronic device is powered on, the processor is configured to output the power-on signal to the driving controller,

wherein the driving controller is configured to output a reset signal to the gate driving circuit for initializing the gate driving circuit in response to the power-on signal, to output a start signal, a first clock signal and a second clock signal for operating the gate driving circuit in response to the input control signal,

wherein the gate driving circuit includes:

a first control circuit configured to control a voltage of a first control node based on an input signal, the first clock signal and the second clock signal;

a second control circuit configured to control a voltage of a second control node based on the first clock signal and the second clock signal;

a reset circuit configured to initialize the first control node and the second control node based on the reset signal; and

an output circuit configured to output the first clock signal or a first voltage as the gate signal based on the voltage of the first control node and the voltage of the second control node,

wherein the second control circuit includes:

a switching circuit connected to a first node and a second node, and configured to receive the second clock signal;

a second capacitor including a first electrode connected to the first node and a second electrode connected to the second node; and

a fourth capacitor including a first electrode configured to receive a second voltage and a second electrode connected to the second node.

18 . The electronic device of claim 17 , wherein the switching circuit includes:

a sixth transistor including a control electrode connected to the first node, a first electrode connected to a third node and a second electrode configured to receive the second clock signal; and

a seventh transistor including a control electrode connected to the first node, a first electrode connected to the second node and a second electrode connected to the third node.

19 . The electronic device of claim 17 , wherein the second control circuit further includes:

a third transistor including a control electrode configured to receive the first clock signal, a first electrode configured to receive the first voltage and a second electrode connected to a fifth node;

a fourth transistor including a control electrode configured to receive the first voltage, a first electrode connected to the fifth node and a second electrode connected to the first node;

a fifth transistor including a control electrode connected to the first control node, a first electrode configured to receive the first clock signal and a second electrode connected to the fifth node;

an eighth transistor including a control electrode configured to receive the second clock signal, a first electrode connected to the second node and a second electrode connected to the second control node; and

a first capacitor including a first electrode configured to receive the first clock signal and a second electrode connected to the second control node.

20 . The electronic device of claim 17 , wherein the first control circuit includes:

a first transistor including a control electrode configured to receive the first clock signal, a first electrode configured to receive the input signal and a second electrode connected to a fourth node;

a second transistor including a control electrode connected to the first control node, a first electrode connected to a sixth node and a second electrode configured to receive the second clock signal;

an eleventh transistor including a control electrode configured to receive the first voltage, a first electrode connected to the fourth node and a second electrode connected to the first control node; and

a third capacitor including a first electrode connected to the first control node and a second electrode connected to the sixth node.