Pixel circuit, display device including the pixel circuit, and electronic device including the display device
A pixel circuit includes first to fifth transistors, a first capacitor, a second capacitor, and a light emitting element. The pixel circuit may provide a high PPI and have a relatively small area or footprint. The pixel circuit may compensate a threshold voltage of the first transistor, a dispersion of a mobility of the first transistor, and a threshold voltage of the third transistor. The pixel circuit may prevent an anode initialization issue due to a body effect from occurring. The pixel circuit may provide an increase in a data swing range. A feedback path formed in the pixel circuit may prevent a deterioration of the light emitting element.
1 . A pixel circuit comprising:
a first transistor comprising a gate electrode connected to a first node, a first electrode which receives a first power supply voltage, and a second electrode connected to a second node;
a second transistor comprising a gate electrode which receives a data write gate signal, a first electrode connected to a data line via which a data voltage is transmitted, and a second electrode connected to the first node;
a third transistor comprising a gate electrode connected to the second node, a first electrode connected to the second node, and a second electrode connected to a third node;
a fourth transistor comprising a gate electrode which receives an emission signal, a first electrode connected to the third node, and a second electrode connected to a fourth node;
a fifth transistor comprising a gate electrode which receives an anode initialization gate signal, a first electrode which receives an initialization voltage, and a second electrode connected to the fourth node;
a first capacitor comprising a first electrode which receives the first power supply voltage and a second electrode connected to the first node; and
a light emitting element comprising an anode connected to the fourth node and a cathode which receives a second power supply voltage.
2 . The pixel circuit of claim 1 , further comprising:
a second capacitor comprising a first electrode connected to the first node and a second electrode connected to the third node.
3 . The pixel circuit of claim 1 , further comprising:
a second capacitor comprising a first electrode connected to the first node and a second electrode connected to the fourth node.
4 . The pixel circuit of claim 1 , wherein the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are NMOS transistors.
5 . The pixel circuit of claim 1 , wherein, in a first duration, the data write gate signal has a high level, the emission signal has a low level, and the anode initialization gate signal has the high level.
6 . The pixel circuit of claim 5 , wherein, in the first duration, the first transistor, the second transistor, the third transistor, and the fifth transistor are turned on, and the fourth transistor is turned off.
7 . The pixel circuit of claim 5 , wherein, in a second duration after the first duration, the data write gate signal has the low level, the emission signal has the high level, and the anode initialization gate signal has the high level.
8 . The pixel circuit of claim 7 , wherein, in the second duration, the first transistor, the third transistor, the fourth transistor, and the fifth transistor are turned on, and the second transistor is turned off.
9 . The pixel circuit of claim 7 , wherein, in a third duration after the second duration, the data write gate signal has the low level, the emission signal has the high level, and the anode initialization gate signal has the low level.
10 . The pixel circuit of claim 9 , wherein, in the third duration, the first transistor, the third transistor, and the fourth transistor are turned on, and the second transistor and the fifth transistor are turned off.
11 . A display device comprising:
a display panel comprising a pixel circuit;
a data driver which provides a data voltage to the pixel circuit;
a gate driver which provides a gate signal to the pixel circuit; and
a driving controller which controls the data driver and the gate driver,
wherein the pixel circuit comprises:
a first transistor comprising a gate electrode connected to a first node, a first electrode which receives a first power supply voltage, and a second electrode connected to a second node;
a second transistor comprising a gate electrode which receives a data write gate signal, a first electrode connected to a data line via which a data voltage is transmitted, and a second electrode connected to the first node;
a third transistor comprising a gate electrode connected to the second node, a first electrode connected to the second node, and a second electrode connected to a third node;
a fourth transistor comprising a gate electrode which receives an emission signal, a first electrode connected to the third node, and a second electrode connected to a fourth node;
a fifth transistor comprising a gate electrode which receives an anode initialization gate signal, a first electrode which receives an initialization voltage, and a second electrode connected to the fourth node;
a first capacitor comprising a first electrode which receives the first power supply voltage and a second electrode connected to the first node; and
a light emitting element comprising an anode connected to the fourth node and a cathode which receives a second power supply voltage.
12 . The display device of claim 11 , wherein the pixel circuit comprises:
a second capacitor comprising a first electrode connected to the first node and a second electrode connected to the third node.
13 . The display device of claim 11 , wherein the pixel circuit comprises:
a second capacitor comprising a first electrode connected to the first node and a second electrode connected to the fourth node.
14 . The display device of claim 11 , wherein the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are NMOS transistors.
15 . The display device of claim 11 , wherein, in a first duration, the data write gate signal has a high level, the emission signal has a low level, and the anode initialization gate signal has the high level.
16 . The display device of claim 15 , wherein, in the first duration, the first transistor, the second transistor, the third transistor, and the fifth transistor are turned on, and the fourth transistor is turned off.
17 . The display device of claim 15 , wherein, in a second duration after the first duration, the data write gate signal has the low level, the emission signal has the high level, and the anode initialization gate signal has the high level.
18 . The display device of claim 17 , wherein, in the second duration, the first transistor, the third transistor, the fourth transistor, and the fifth transistor are turned on, and the second transistor is turned off.
19 . The display device of claim 17 , wherein, in a third duration after the second duration, the data write gate signal has the low level, the emission signal has the high level, and the anode initialization gate signal has the low level.
20 . An electronic device comprising:
a display panel comprising a pixel circuit;
a data driver which provides a data voltage to the pixel circuit;
a gate driver which provides a gate signal to the pixel circuit;
a driving controller which controls the data driver and the gate driver; and
a processor which controls the driving controller,
wherein the pixel circuit comprises:
a first transistor comprising a gate electrode connected to a first node, a first electrode which receives a first power supply voltage, and a second electrode connected to a second node;
a second transistor comprising a gate electrode which receives a data write gate signal, a first electrode connected to a data line via which a data voltage is transmitted, and a second electrode connected to the first node;
a third transistor comprising a gate electrode connected to the second node, a first electrode connected to the second node, and a second electrode connected to a third node;
a fourth transistor comprising a gate electrode which receives an emission signal, a first electrode connected to the third node, and a second electrode connected to a fourth node;
a fifth transistor comprising a gate electrode which receives an anode initialization gate signal, a first electrode which receives an initialization voltage, and a second electrode connected to the fourth node;
a first capacitor comprising a first electrode which receives the first power supply voltage and a second electrode connected to the first node; and
a light emitting element comprising an anode connected to the fourth node and a cathode which receives a second power supply voltage.