Pixel driving circuit, driving method thereof and display device

1 . A pixel driving circuit, wherein the pixel driving circuit in an n th row comprises:

a reset sub-circuit electrically connected with a first reset signal line, a first scanning signal line, a first node, a second reset signal line, a second scanning signal line and a second node, wherein the reset sub-circuit is configured to reset a voltage of the first node under the control of a first scanning signal, and further configured to reset a voltage of the second node under the control of a second scanning signal;

a data writing sub-circuit electrically connected with a data line, a third scanning signal line and the second node, wherein the data writing sub-circuit is configured to write a data signal transmitted by the data line into the second node;

a driving transistor, wherein a gate of the driving transistor is electrically connected with the second node, a first electrode of the driving transistor is electrically connected with a third node, a second electrode of the driving transistor is electrically connected with the first node, and the driving transistor is configured to generate a driving current under the control of the voltage of the second node;

a first emission control sub-circuit electrically connected with a first emission control signal line, a first power supply line and the third node, wherein the first emission control sub-circuit is configured to transmit a first power supply signal to the driving transistor under the control of a first emission control signal;

a second emission control sub-circuit electrically connected with a second emission control signal line, the first node and an anode of a light emitting device respectively, wherein the second emission control sub-circuit is configured to transmit the driving current to the anode under the control of a second emission control signal;

a storage sub-circuit electrically connected with the first node, the second node and the first power supply line, wherein the storage sub-circuit is configured to store the voltage of the second node and adjust the voltage of the first node; and

an anode reset sub-circuit electrically connected with the anode, a fourth scanning signal line and a second power supply line, wherein the anode reset sub-circuit is configured to reset the anode under the control of a fourth scanning signal;

wherein n is a positive integer, and the first scanning signal line, the third scanning signal line and the fourth scanning signal line are gate lines in different rows.

2 . The pixel driving circuit according to claim 1 , wherein pulse widths of scanning signals loaded on the first scanning signal, the third scanning signal and the fourth scanning signal are the same;

wherein the first scanning signal line is an (n−4) th gate line, the third scanning signal line is an n th gate line, and the fourth scanning signal line is an (n+2) th gate line;

wherein the n th gate line is electrically connected with the n th row of pixel driving circuits, an n th second scanning signal line is electrically connected with the n th row of pixel driving circuits, and n is greater than 4;

wherein an m th row of pixel driving circuits are dummy pixel driving circuits, m is a positive integer, and m is greater than or equal to 1 and less than or equal to 4, and is equal to n+1 or n+2;

wherein the m th row of pixel driving circuits are electrically connected with a shifting register in an m th row.

3 . The pixel driving circuit according to claim 1 , wherein the first reset signal line comprises a reference signal line, the second reset signal line comprises an initialization signal line, and an absolute value of a difference between a voltage of a reference signal transmitted by the reference signal line and a voltage of an initialization signal transmitted by the initialization signal line is greater than a threshold voltage of the driving transistor.

4 . The pixel driving circuit according to claim 1 , wherein the first reset signal line comprises the first power supply line, and the second reset signal line comprises the second power supply line.

5 . The pixel driving circuit according to claim 1 , wherein the data writing sub-circuit comprises a first transistor, a gate of the first transistor is electrically connected with the third scanning signal line, a first electrode of the first transistor is electrically connected with the data line, and a second electrode of the first transistor is electrically connected with the gate of the driving transistor through the second node, wherein a switching transistor is further arranged in series between the data line and the first transistor, and the switching transistor is configured to write the data signal into the data line before the first transistor is turned on; or

the data writing sub-circuit comprises a first transistor and a seventh transistor, a gate of the first transistor is electrically connected with the third scanning signal line, a first electrode of the first transistor is electrically connected with the data line, and a second electrode of the first transistor is electrically connected with a first electrode of the seventh transistor; and a gate of the seventh transistor is electrically connected with the second scanning signal line, and a second electrode of the seventh transistor is electrically connected with the gate of the driving transistor through the second node.

6 . The pixel driving circuit according to claim 5 , wherein the reset sub-circuit comprises a second transistor and a fourth transistor; and

a gate of the second transistor is electrically connected with the second scanning signal line, a first electrode of the second transistor is electrically connected with the first reset signal line, and a second electrode of the second transistor is electrically connected with the gate of the driving transistor through the second node; and a gate of the fourth transistor is electrically connected with the first scanning signal line, a first electrode of the fourth transistor is electrically connected with the second reset signal line, and a second electrode of the fourth transistor is electrically connected with the first node.

7 . The pixel driving circuit according to claim 6 , wherein the first emission control sub-circuit comprises a third transistor;

wherein a gate of the third transistor is electrically connected with the first emission control signal line, a first electrode of the third transistor is electrically connected with the first power supply line, and a second electrode of the third transistor is electrically connected with the third node.

8 . The pixel driving circuit according to claim 7 , wherein the second emission control sub-circuit comprises a fifth transistor;

wherein a gate of the fifth transistor is electrically connected with the second emission control signal line, a first electrode of the fifth transistor is electrically connected with the first node, and a second electrode of the fifth transistor is electrically connected with the anode.

9 . The pixel driving circuit according to claim 8 , wherein the storage sub- circuit comprises a first capacitor and a second capacitor;

wherein a first electrode of the first capacitor is electrically connected with the second node, and a second electrode of the first capacitor is electrically connected with the first node; and a first electrode of the second capacitor is electrically connected with the first power supply line, and a second electrode of the second capacitor is electrically connected with the second electrode of the first capacitor through the first node.

10 . The pixel driving circuit according to claim 9 , wherein the anode reset sub-circuit comprises a sixth transistor;

wherein a gate of the sixth transistor is electrically connected with the fourth scanning signal line, a first electrode of the sixth transistor is electrically connected with the anode, and a second electrode of the sixth transistor is electrically connected with the second power supply line and a cathode of the light emitting device respectively.

11 . The pixel driving circuit according to claim 10 , wherein, when the data writing sub-circuit comprises the first transistor, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor and the driving transistor are all N-type transistors; and

when the data writing sub-circuit comprises the first transistor and the seventh transistor, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor and the driving transistor are all N-type transistors, and the seventh transistor is a P-type transistor.

12 . The pixel driving circuit according to claim 3 , wherein when the driving transistor is a N-type transistor, the voltage of the reference signal is greater than the voltage of the initialization signal, wherein the absolute value of the difference between the voltage of the reference signal and the voltage of the initialization signal ranges from 2 V to 4 V.

13 . The pixel driving circuit according to claim 2 , wherein a rising edge of a pulse signal transmitted by the second scanning signal coincides with a rising edge of a pulse signal transmitted by the first scanning signal, and a falling edge of the pulse signal transmitted by the second scanning signal coincides with a rising edge of a pulse signal transmitted by the third scanning signal, or the falling edge of the pulse signal transmitted by the second scanning signal is located behind the rising edge of the pulse signal transmitted by the third scanning signal.

14 . The pixel driving circuit according to claim 13 , wherein a scanning time of the third scanning signal is greater than a scanning time of the second scanning signal; or

an overlapping time of the first emission control signal and the second scanning signal is greater than the overlapping time of the third scanning signal and the second scanning signal.

15 . The pixel driving circuit according to claim 1 , wherein the first emission control signal comprises a first pulse signal and a second pulse signal, the second emission control signal comprises a third pulse signal, and the second pulse signal coincides with the third pulse signal.

16 . The pixel driving circuit according to claim 9 , wherein a capacitance value of the second capacitor is less than a capacitance value of the first capacitor.

17 . The pixel driving circuit according to claim 10 , wherein the first transistor, the second transistor, the fourth transistor and the fifth transistor are all double-gate transistors; and two gates of the same transistor are electrically connected together; or

the first transistor, the second transistor, the fourth transistor and the fifth transistor are all metal oxide transistors.

18 . The pixel driving circuit according to claim 1 , wherein the driving transistor is a double-gate transistor, one gate of the driving transistor is electrically connected with the second node, the other gate of the driving transistor is electrically connected with a signal input end with a constant voltage, and the constant voltage is less than a threshold voltage of the driving transistor.

19 . A display device, comprising the pixel driving circuit according to claim 1 .

20 . A driving method, applied to the pixel driving circuit according to claim 1 , wherein the method comprises:

in a first stage, inputting a first emission control signal at low level to the first emission control signal line, inputting a second emission control signal at low level to the second emission control signal line, inputting a first scanning signal at high level to the first scanning signal line, inputting a second scanning signal at high level to the second scanning signal line, inputting a third scanning signal at low level to the third scanning signal line, and inputting a fourth scanning signal at low level to the fourth scanning signal line;

in a second stage, inputting a first emission control signal at high level to the first emission control signal line, inputting the second emission control signal at low level to the second emission control signal line, inputting a first scanning signal at low level to the first scanning signal line, inputting the second scanning signal at high level to the second scanning signal line, inputting the third scanning signal at low level to the third scanning signal line, and inputting the fourth scanning signal at low level to the fourth scanning signal line;

in a third stage, inputting the first emission control signal at low level to the first emission control signal line, inputting the second emission control signal at low level to the second emission control signal line, inputting the first scanning signal at low level to the first scanning signal line, inputting a second scanning signal at low level to the second scanning signal line, inputting a third scanning signal at high level to the third scanning signal line, and inputting the fourth scanning signal at low level to the fourth scanning signal line;

in a fourth stage, inputting a first emission control signal at low level to the first emission control signal line, inputting the second emission control signal at low level to the second emission control signal line, inputting a first scanning signal at low level to the first scanning signal line, inputting a second scanning signal at low level to the second scanning signal line, inputting the third scanning signal at low level to the third scanning signal line, and inputting a fourth scanning signal at high level to the fourth scanning signal line; and

in a fifth stage, inputting the first emission control signal at high level to the first emission control signal line, inputting a second emission control signal at high level to the second emission control signal line, inputting a first scanning signal at low level to the first scanning signal line, inputting the second scanning signal at low level to the second scanning signal line, inputting the third scanning signal at low level to the third scanning signal line, and inputting the fourth scanning signal at low level to the fourth scanning signal line.