Display panel and display apparatus
Provided are a display panel and a display apparatus. A shift register in the display panel includes N shift register units connected in cascade. At least one of the shift register units includes a driving module and a gating module. The gating module is configured to receive a signal output by the driving module and a sweep frequency control signal, and output a sweep signal. The sweep frequency control signal and the sweep frequency signal each includes a ramp signal, a period of the sweep frequency control signal is n*H, where H is a scanning time of one row of pixels, and n≥2. In the period of the sweep frequency control signal, a width of the ramp signal in the sweep frequency control signal is (n−1)*H+A, and 0<A<H.
1 . A display panel, comprising a shift register, wherein the shift register comprises N shift register units connected in cascade, at least one of the shift register units comprises a driving module and a gating module, and one control terminal of the gating module is connected to an output terminal of the driving module, and the output terminal of the driving module in an i-th stage shift register unit is connected to an input terminal of the driving module in an (i+1)-th stage shift register unit, wherein i and N are integers, and 1≤i<N;
the gating module is configured to at least receive a signal output by the driving module and a sweep frequency control signal, and output a sweep frequency signal, the sweep frequency control signal and the sweep frequency signal each comprises a ramp signal, and a period of the sweep frequency control signal is n*H, wherein His a scanning time of one row of pixels, n is an integer, and n≥2; and
wherein in the period of the sweep frequency control signal, a width of the ramp signal in the sweep frequency control signal is (n−1)*H+A, and 0<A<H.
2 . The display panel according to claim 1 , wherein the input terminal of the driving module in a first-stage shift register unit receives a start signal, and a width of an effective level in the start signal is to, and t 0 ≥(n−1)*H+A.
3 . The display panel according to claim 2 , wherein n is an even number, and t 0 =(n+1)*H.
4 . The display panel according to claim 1 , wherein the ramp signal in the sweep frequency signal comprises a first ramp signal and a second ramp signal, a width of the first ramp signal is (n−1)*H+A, and a width of the second ramp signal is smaller than the width of the first ramp signal.
5 . The display panel according to claim 4 , wherein the width of the second ramp signal is smaller than H.
6 . The display panel according to claim 4 , further comprising a pixel circuit, wherein the pixel circuit comprises a first driving circuit and a second driving circuit, the first driving circuit is configured to control an amplitude of a driving current provided to a sub-pixel based on a first data voltage, and the second driving circuit is configured to control a duration of the driving current provided to the sub-pixel based on a second data voltage;
an output terminal of the gating module is connected to the second driving circuit;
the first driving circuit comprises a first driving transistor, a first control transistor, and a second control transistor, the first driving transistor is connected in series between the first control transistor and the second control transistor, and a control terminal of the first control transistor and/or a control terminal of the second control transistor receives a first control signal; and
during operation of the pixel circuit, a time period of an effective level in the first control signal does not overlap with the second ramp signal.
7 . The display panel according to claim 6 , wherein during operation of the pixel circuit, an end time of the effective level in the first control signal is not later than a start time of the second ramp signal.
8 . The display panel according to claim 6 , wherein during operation of the pixel circuit, a start time of the first ramp signal is earlier than a start time of the effective level in the first control signal.
9 . The display panel according to claim 8 , wherein during operation of the pixel circuit, a duration between the start time of the first ramp signal and the start time of the effective level in the first control signal is t 1 , and a duration between the start time of the effective level in the first control signal and an end time of the first ramp signal is t 2 , wherein t 1 <t 2 .
10 . The display panel according to claim 9 , wherein t 1 ≥H.
11 . The display panel according to claim 9 , wherein H<t 2 ≤(n−2)*H+A.
12 . The display panel according to claim 6 , wherein a width of the effective level in the first control signal is (n−1)*H.
13 . The display panel according to claim 6 , wherein the input terminal of the driving module in a first-stage shift register unit receives a start signal; and
a width of an effective level in the start signal is greater than a width of the effective level in the first control signal.
14 . The display panel according to claim 6 , wherein the second driving circuit comprises a second driving transistor, a third control transistor, and a fourth control transistor, the second driving transistor is connected in series between the third control transistor and the fourth control transistor, and a control terminal of the third control transistor and/or a control terminal of the fourth control transistor receives a second control signal;
during operation of the pixel circuit, a width of an effective level in the second control signal is greater than a width of the effective level in the first control signal.
15 . The display panel according to claim 14 , wherein during operation of the pixel circuit, a start time of the effective level in the second control signal is earlier than a start time of the effective level in the first control signal.
16 . The display panel according to claim 6 , wherein during operation of the pixel circuit, an end time of the effective level in the second control signal is later than an end time of the effective level in the first control signal.
17 . The display panel according to claim 6 , wherein the second driving circuit comprises a second driving transistor, a third control transistor, and a fourth control transistor, the second driving transistor is connected in series between the third control transistor and the fourth control transistor, and a control terminal of the third control transistor and/or a control terminal of the fourth control transistor receives a second control signal; and
during operation of the pixel circuit, a width of an effective level in the second control signal is greater than a sum of the width of the first ramp signal and the width of the second ramp signal in the sweep frequency signal.
18 . The display panel according to claim 1 , further comprising n sweep frequency control signal lines, wherein at least one of the sweep frequency control signal lines provides the sweep frequency control signal, the n sweep frequency control signal lines comprise a first sweep frequency control signal line, a second sweep frequency control signal line, to a n-th sweep frequency control signal line arranged in sequence; and period start times of sweep frequency control signals provided by two adjacent sweep frequency control signal lines in the sequence differ by H; and
wherein the gating module in a j-th stage shift register unit and the gating module in a (n*m+j)-th stage shift register unit are connected to a j-th sweep frequency control signal line, wherein j and m are integers, 1≤j≤n, and 1≤m≤(N/n)−1.
19 . The display panel according to claim 1 , wherein the driving module comprises a first transistor and a second transistor, a control terminal of the first transistor is connected to a first node, and a control terminal of the second transistor is connected to a second node, the first transistor provides a first voltage signal to the output terminal of the driving module under the control of a potential of the first node, and the second transistor provides a second voltage signal to the output terminal of the driving module under the control of a potential of the second node; and
the gating module comprises a third transistor and a fourth transistor, a control terminal of the third transistor is connected to the output terminal of the driving module, and a control terminal of the fourth transistor is connected to the first node, a first terminal of the third transistor receives the sweep frequency control signal, a first terminal of the fourth transistor receives a third voltage signal, and a second terminal of the third transistor and a second terminal of the fourth transistor are connected to the output terminal of the gating module.
20 . A display apparatus, comprising a display panel;
wherein the display panel comprises a shift register, wherein the shift register comprises N shift register units connected in cascade, at least one of the shift register units comprises a driving module and a gating module, and one control terminal of the gating module is connected to an output terminal of the driving module, and the output terminal of the driving module in an i-th stage shift register unit is connected to an input terminal of the driving module in an (i+1)-th stage shift register unit, wherein i and N are integers, and 1≤i<N;
the gating module is configured to at least receive a signal output by the driving module and a sweep frequency control signal, and output a sweep frequency signal, the sweep frequency control signal and the sweep frequency signal each comprises a ramp signal, and a period of the sweep frequency control signal is n*H, wherein H is a scanning time of one row of pixels, n is an integer, and n≥2; and
wherein in the period of the sweep frequency control signal, a width of the ramp signal in the sweep frequency control signal is (n−1)*H+A, and 0<A<H.