Display device and electronic device including the same
Provided is a display device including a light emitting element, a first transistor including a first electrode, a second electrode connected to an anode of the light emitting element, and a control electrode connected to a first node, a second transistor including a first electrode connected to a data line, a second electrode connected to the first electrode of the first transistor, and a control electrode connected to a write scan line, a fifth transistor including a first electrode connected to a first power line, a second electrode connected to the first electrode of the first transistor, and a control electrode connected to an emission line, and a doped region including a semiconductor doped with a dopant, disposed below a portion of the emission line, and overlapping the emission line in a plan view.
1 . A display device comprising:
a light emitting element;
a first transistor comprising a first electrode, a second electrode connected to an anode of the light emitting element, and a control electrode connected to a first node;
a second transistor comprising a first electrode connected to a data line, a second electrode connected to the first electrode of the first transistor, and a control electrode connected to a write scan line;
a fifth transistor comprising a first electrode connected to a first power line, a second electrode connected to the first electrode of the first transistor, and a control electrode connected to an emission line; and
a doped region comprising a semiconductor doped with a dopant to be highly conductive, disposed below a portion of the emission line, and overlapping the emission line in a plan view.
2 . The display device of claim 1 , wherein the doped region is disposed between a first semiconductor layer of the first transistor and a fifth semiconductor layer of the fifth transistor.
3 . The display device of claim 2 , wherein the doped region extends from the first semiconductor layer to the fifth semiconductor layer and is formed integrally with the first and fifth semiconductor layers.
4 . The display device of claim 2 , wherein the doped region has a higher conductivity than a first channel region of the first semiconductor layer.
5 . The display device of claim 4 , wherein a first source region and a first drain region of the first semiconductor layer correspond to the first electrode and the second electrode of the first transistor, respectively, and
wherein a doping concentration of the doped region is different from a doping concentration of each of the first source region and the first drain region.
6 . The display device of claim 5 , wherein the doped region is doped before the first source region and the first drain region is doped.
7 . The display device of claim 1 , wherein the doped region is doped with a p-type dopant.
8 . The display device of claim 1 , wherein the emission line is disposed on the same layer as the control electrode of the fifth transistor.
9 . The display device of claim 8 , wherein the control electrode of the fifth transistor is formed at the same time with the emission line.
10 . The display device of claim 1 , further comprising:
a third transistor comprising a first electrode connected to the second electrode of the first transistor, a second electrode connected to the first node, and a control electrode connected to a compensation scan line; and
a fourth transistor comprising a first electrode connected to the first node, a second electrode connected to a first initialization line, and a control electrode connected to an initialization scan line.
11 . The display device of claim 10 , wherein the first initialization line is disposed above the fourth transistor.
12 . The display device of claim 11 , wherein a fourth source region and a fourth drain region of a fourth semiconductor layer of the fourth transistor correspond to the second electrode and the first electrode of the fourth transistor, respectively, and
wherein the first initialization line is connected to the fourth semiconductor layer through a single contact hole defined in insulating layers disposed between the first initialization line and the fourth semiconductor layer.
13 . The display device of claim 10 , wherein a third semiconductor layer of the third transistor and a fourth semiconductor layer of the fourth transistor are formed integrally and extend in a first direction,
wherein the compensation scan line and the initialization scan line extend in a second direction crossing the first direction and are arranged in the first direction, and
wherein the compensation scan line extends to intersect the third semiconductor layer, and the initialization scan line extends to intersect the fourth semiconductor layer.
14 . The display device of claim 13 , wherein a length of each of a third channel region of the third semiconductor layer which overlaps the compensation scan line and a fourth channel region of the fourth semiconductor layer which overlaps the initialization scan line in the first direction is set to be about 3.5 micrometers.
15 . The display device of claim 14 , wherein a width of each of the third channel region and the fourth channel region in the second direction is set to be about 3.0 micrometers.
16 . The display device of claim 13 , further comprising:
a sixth transistor comprising a first electrode connected to the second electrode of the first transistor, a second electrode connected to the anode of the light emitting element, and a control electrode connected to the emission line; and
a seventh transistor comprising a first electrode connected to the anode of the light emitting element, a second electrode connected to a second initialization line, and a control electrode connected to a bias scan line.
17 . The display device of claim 16 , further comprising a first pixel circuit and a second pixel circuit, each of which comprises the first to seventh transistors and the light emitting element, and which are adjacent to each other in the second direction,
wherein, in the second direction, a gap between third and fourth semiconductor layers of the first pixel circuit, and third and fourth semiconductor layers of the second pixel circuit is set to be about 2.5 micrometers to about 3.5 micrometers.
18 . The display device of claim 17 , wherein the seventh transistors of the first and second pixel circuits are connected to the second initialization line through a single contact hole, and
wherein the single contact hole is defined in insulating layers between seventh semiconductor layers of the seventh transistors and the second initialization line.
19 . A display device comprising: a light emitting element; a first transistor comprising a first electrode, a second electrode connected to an anode of the light emitting element, and a control electrode connected to a first node; a second transistor comprising a first electrode connected to a data line, a second electrode connected to the first electrode of the first transistor, and a control electrode connected to a write scan line; a fifth transistor comprising a first electrode connected to a first power line, a second electrode connected to the first electrode of the first transistor, and a control electrode connected to an emission line; and a doped region comprising a semiconductor doped with a dopant to be highly conductive, disposed below a portion of the emission line, and overlapping the emission line in a plan view, wherein the emission line is disposed on the same layer as the control electrode of the fifth transistor.
20 . An electronic device comprising: a processor; and a display device receiving image data from the processor and configured to display an image corresponding to the image data, wherein the display device comprises: a light emitting element; a first transistor comprising a first electrode, a second electrode connected to an anode of the light emitting element, and a control electrode connected to a first node; a second transistor comprising a first electrode connected to a data line, a second electrode connected to the first electrode of the first transistor, and a control electrode connected to a write scan line; a fifth transistor comprising a first electrode connected to a first power line, a second electrode connected to the first electrode of the first transistor, and a control electrode connected to an emission line; and a doped region comprising a semiconductor doped with a dopant to be highly conductive, disposed below a portion of the emission line, and overlapping the emission line in a plan view.