Gate driving circuit and display device
Embodiments of the present disclosure are related to a gate driving circuit and a display device. Specifically, a compensation signal corresponding to a change in gate low voltage in a scan period may be applied to at least one gate line among the plurality of gate lines in each of at least one compensation period excluding a scan period during which the scan signal is applied to the plurality of gate lines during the display driving period. Accordingly, it is possible to provide a gate driving circuit and a display device capable of implementing low-power driving and improved image quality by reducing flicker due to the decrease in luminance during low-speed driving.
1 . A display device comprising:
a display panel on which a plurality of gate lines, a plurality of data lines and a plurality of subpixels are disposed;
a gate driving circuit for supplying a scan signal to the plurality of gate lines during a display driving period; and
a data driving circuit for supplying a data voltage to the plurality of data lines,
wherein the gate driving circuit is configured to apply a compensation signal corresponding to a change in a gate low voltage in a scan period to at least one gate line among the plurality of gate lines in each of at least one compensation period excluding a scan period during which the scan signal is applied to the plurality of gate lines during the display driving period, and
wherein the scan period and the compensation period each include a blank period, and a length of a blank period included in the scan period is equal to a length of a blank period included in the compensation period.
2 . The display device of claim 1 , wherein a length of the compensation period is equal to a length of the scan period.
3 . The display device of claim 1 , wherein the scan period includes a blank period and a low voltage rising period in which a gate low voltage increases at a node to which the scan signal is applied due to an influence of a parasitic capacitor before and after a timing at which the scan signal is applied to the plurality of gate lines.
4 . The display device of claim 1 , wherein the scan period includes a refresh frame period corresponding to the timing at which the scan signal is applied, and at least one anode reset frame period.
5 . The display device of claim 1 , wherein each of the plurality of subpixels includes a driving transistor and a first transistor connecting a second node corresponding to a gate electrode of the driving transistor and a third node corresponding to a second electrode of the driving transistor,
wherein the gate driving circuit is configured to supply the scan signal and the compensation signal to a gate node of the first transistor.
6 . The display device of claim 1 , wherein the gate driving circuit includes at least one gate-in-panel circuit disposed in the display panel.
7 . The display device of claim 1 , wherein the gate driving circuit is configured to receive gate voltages and the compensation signal from a driver integrated circuit disposed outside the display panel, and to generate the scan signal based on the gate voltages.
8 . The display device of claim 7 , wherein the driver integrated circuit is configured to generate the compensation signal based on the gate low voltage among the gate voltages.
9 . A display device comprising:
a display panel on which a plurality of gate lines, a plurality of data lines and a plurality of subpixels are disposed;
a gate driving circuit for supplying a scan signal to the plurality of gate lines during a display driving period; and
a data driving circuit for supplying a data voltage to the plurality of data lines,
wherein the gate driving circuit is configured to apply a compensation signal corresponding to a change in a gate low voltage in a scan period to at least one gate line among the plurality of gate lines in each of at least one compensation period excluding a scan period during which the scan signal is applied to the plurality of gate lines during the display driving period, and
wherein a voltage level of the compensation signal is a median value of an increased gate low voltage level in the scan period corresponding to each of the plurality of gate lines.
10 . A display device comprising:
a display panel on which a plurality of gate lines, a plurality of data lines and a plurality of subpixels are disposed; and
a gate driving circuit configured to supply a gate signal to the plurality of gate lines based on a gate high voltage and a gate low voltage,
wherein the gate driving circuit is configured to supply the gate signal including a first signal section having a variable gate high voltage higher than the gate high voltage, a second signal section having the gate low voltage at a first voltage level, and a third signal section having the gate low voltage at a second voltage level higher than the first voltage level,
wherein the gate signal is supplied during a display driving period including a scan period and at least one compensation period, the scan period including the first signal section and the second signal section, and the at least one compensation period including the third signal section and the second signal section, and wherein a length of the second signal section included in the scan period is equal to a length of the second signal section included in the at least one compensation period.