IP Library Granted Patent US 12706054
Granted Patent B2
US 12706054 · App. 19/228,031 · Granted Aug 11, 2026

Display device

Inventors: Tatsuya Ishii (Tokyo, JP); Kenji Harada (Tokyo, JP)
Assignee: Japan Display Inc.
G09G3/3266G09G2300/0426G09G2300/0819G09G2310/0251G09G2310/0286G09G2310/08G09G2330/021
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Quick Facts
Patent No.
US 12706054
App. No.
19/228,031
Granted
Aug 11, 2026
Kind
B2
Abstract

A display device includes a first transistor connected between an image data signal line and a first node, switching of the first transistor controlled by a first control signal, a third transistor connected between the first node and a second node, switching of the third transistor controlled by a second control signal, a second transistor connected to the second node and connected between a power line and the third node, a fourth transistor connected between a reference voltage power line and the second node, switching of the fourth transistor controlled by the second control signal, a fifth transistor connected between an initialization voltage power line and the third node, switching of the fifth transistor controlled by the third control signal, and a sixth transistor electrically connected between a pre-charge voltage power line and the first node, and switching of the sixth transistor controlled by the fourth control signal.

Claims (90)

1 . A display device comprising:

a first transistor electrically connected between an image data signal line and a first node, the switching of the first transistor is controlled by a first control signal, and a data voltage is supplied to the image data signal line;

a third transistor electrically connected between the first node and a second node, the switching of the third transistor is controlled by a second control signal, and the second control signal is different from the first control signal;

a second transistor including a gate electrode electrically connected to the second node and electrically connected between a power line and a third node, and a constant voltage is supplied to the power line;

a fourth transistor electrically connected between a reference voltage power line and the second node, the switching of the fourth transistor is controlled by the second control signal, and a reference voltage is supplied to the reference voltage power line;

a fifth transistor electrically connected between an initialization voltage power line and the third node, the switching of the fifth transistor is controlled by a third control signal, the third control signal is different from the first control signal and the second control signal, and an initialization voltage is supplied to the initialization voltage power line;

a sixth transistor electrically connected between a pre-charge voltage power line and the first node, the switching of the sixth transistor is controlled by a fourth control signal, the fourth control signal is different from the first control signal and the second control signal, and a pre-charge voltage is supplied to the pre-charge voltage power line;

a light-emitting element electrically connected to the third node; and

a capacitive element electrically connected between the first node and the third node.

2 . The display device according to claim 1 , further comprising:

a fifth control signal line,

wherein

the fifth control signal line serves as both the reference voltage power line and the initialization voltage power line.

3 . The display device according to claim 1 , further comprising:

a sixth control signal line,

wherein

the sixth control signal line serves as both a third control signal line and a fourth control signal line, the third control signal is supplied to the third control signal line, and the fourth control signal is supplied to the fourth control signal line.

4 . The display device according to claim 1 , wherein

the third control signal is a signal obtained by shifting the fourth control signal.

5 . The display device according to claim 1 , further comprising:

a control circuit outputting the first control signal, the second control signal, the third control signal, and the fourth control signal,

wherein

the control circuit includes a first period and a second period after the first period,

the control circuit is configured to control outputting a high-level voltage as the fourth control signal, turning on the sixth transistor, outputting a high-level voltage as the first control signal, and the sixth transistor to supply the pre-charge voltage to the first node in the first period, and

the control circuit is configured to control turning on the first transistor, and the first transistor to supply the data voltage to the first node.

6 . The display device according to claim 1 ,

wherein

the first transistor, the second transistor, the fourth transistor, the fifth transistor, and the sixth transistor are n-channel type field effect transistors, and

the third transistor is a p-channel type field effect transistor.

7 . The display device according to claim 1 ,

wherein

the first transistor, the fourth transistor, the fifth transistor, and the sixth transistor are n-channel type field effect transistors, and

the second transistor and the third transistor are p-channel type field effect transistors.

8 . The display device according to claim 1 ,

wherein

a channel length of the second transistor is longer than a channel length of the first transistor, a channel length of the third transistor, a channel length of the fourth transistor, a channel length of the fifth transistor, and a channel length of the sixth transistor.

9 . The display device according to claim 1 , wherein

channel regions of the second transistor, the third transistor, and the fifth transistor each are comprised of crystalline silicon,

channel regions of the first transistor, the fourth transistor, and the sixth transistor each are comprised of an oxide semiconductor, and

the crystalline silicon of the third transistor overlaps the oxide semiconductor of the fourth transistor in a plan view.

10 . The display device according to claim 1 , further comprising:

a first conductive layer, and

a second conductive layer different from the first conductive layer;

wherein

each of the reference voltage power line, the initialization voltage power line, and the pre-charge voltage power line includes the first conductive layer and the second conductive layer different from each other,

the first conductive layer and the second conductive layer included in the reference voltage power line overlap, the first conductive layer and the second conductive layer included in the initialization voltage power line overlap, and the first conductive layer and the second conductive layer included in the pre-charge voltage power line overlap, in a plan view.

11 . The display device according to claim 1 , wherein

the gate electrode overlaps the capacitive element, in a plan view.

12 . A display device comprising:

a first transistor electrically connected between an image data signal line and a first node, the switching of the first transistor is controlled by a first control signal, and a data voltage is supplied to the image data signal line;

a third transistor electrically connected between the first node and a second node, the switching of the third transistor is controlled using the first control signal;

a second transistor including a gate electrode electrically connected to the second node and electrically connected between a power line and a third node, and a constant voltage is supplied to the power line;

a fourth transistor electrically connected between the second node and a third control signal line, the switching of the fourth transistor is controlled by a second control signal, the second control signal is different from the first control signal, the third control signal line is supplied with a third control signal, the third control signal includes a pre-charge voltage, a first initialization voltage and a second initialization voltage, the first initialization voltage is different from a pre-charge voltage, and the second initialization voltage is different from a pre-charge voltage and the first initialization voltage;

a fifth transistor electrically connected between the third control signal line and the third node, the switching of the fifth transistor is controlled by the second control signal and a fourth control signal, and the fourth control signal is different from the first control signal;

a light-emitting element electrically connected to the third node; and

a capacitive element electrically connected between the first node and the third node.

13 . The display device according to claim 12 , further comprising: a control circuit outputting the first control signal, the second control signal, the third control signal, and the fourth control signal,

wherein

the control circuit includes a first period and a second period after the first period,

the control circuit is configured to control outputting a low-level voltage as the first control signal, turning the first transistor off and to turn the third transistor on, supplying a high-level voltage to the second control signal, turning the fourth transistor on, and the fourth transistor to supply the pre-charge voltage to the second node in the first period, and

the control circuit is configured to control outputting a high-level voltage as the first control signal, turning the first transistor on and turning the third transistor off, and the first transistor to supply the data voltage to the first node in the second period.

14 . The display device according to claim 12 , wherein

the first transistor, the second transistor, the fourth transistor, and the fifth transistor are n-channel type field effect transistors, and

the third transistor is a p-channel type field effect transistor.

15 . The display device according to claim 12 , further comprising:

channel regions of the second transistor, the third transistor and the fifth transistor each are comprised of crystalline silicon, and

channel regions of the first transistor and the fourth transistor each are comprised of an oxide semiconductor.

16 . A display device comprising:

a first transistor electrically connected between an image data signal and a first node, the switching of the first transistor is controlled by a first control signal, and a data voltage is supplied to the image data signal line;

a third transistor electrically connected between the first node and a third node, the switching of the third transistor is controlled by a second control signal, and the second control signal is different from the first control signal;

a second transistor including a gate electrode electrically connected to the second node and electrically connected between the third node and a fourth node;

a fourth transistor electrically connected between the third node and a third control signal, the switching of the fourth transistor is controlled by the second control signal, a third control signal is supplied to the third control signal line, the third control signal includes a first initialization voltage and a second initialization voltage, the second initialization voltage is different from the first initialization voltage, and the first initialization voltage is supplied to the third control signal line;

a fifth transistor electrically connected between the third control signal line and the fourth node, the switching of the fifth transistor is controlled by a fourth control signal, and the fourth control signal is different from the first control signal, the second control signal and the third control signal;

a sixth transistor electrically connected between the second node and the fourth node, the switching of the sixth transistor is controlled by using the second control signal;

a seventh transistor electrically connected between a voltage line and the fourth node, the switching of the seventh transistor is controlled by the second control signal, and a constant voltage is supplied to the voltage line;

an eighth transistor electrically connected between a pre-charge voltage power line and the first node, the switching of the eighth transistor is controlled by a fifth control signal, the fifth control signal is different from the first control signal, the second control signal, the third control signal and the fourth control signal, and a pre-charge voltage is supplied to the pre-charge voltage power line;

a light-emitting element electrically connected to the third node; and

a capacitive element electrically connected between the first node and the second node.

17 . The display device according to claim 16 , further comprising:

a control circuit outputting the first control signal, the second control signal, the third control signal, the fourth control signal, and the fifth control signal,

wherein

the control circuit includes a first period and a second period after the first period,

the control circuit is configured to control supplying a low-level voltage to the first control signal, turning off the first transistor, supplying a high-level voltage to the second control signal, turning off the third transistor, supplying a high-level voltage to the fifth control signal, turning on the eighth transistor, and supplying the data voltage to the first node in the first period, and

the control circuit is configured to control supplying a high-level voltage to the first control signal, turning on the first transistor, supplying a high-level voltage to the second control signal, maintaining the third transistor in the off state, supplying a low-level voltage to the fifth control signal, turning off the eighth transistor, and the first transistor to supply the data voltage to the first node.

18 . The display device according to claim 16 , wherein

the first transistor, the second transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the eighth transistor are n-channel type field effect transistors, and

the third transistor and the seventh transistor are p-channel type field effect transistors.

19 . The display device according to claim 18 , wherein

channel regions of the second transistor, the third transistor, the fifth transistor, and the seventh transistor each are comprised of crystalline silicon, and

the channel regions of the first transistor, the fourth transistor, the sixth transistor, and the eighth transistor each are comprised of an oxide semiconductor.