Display apparatus

1 . A display apparatus, comprising:

a display panel including a plurality of pixels; and

a controller configured to control an operation of the display panel,

wherein the controller is configured to:

generate an internal horizontal synchronization signal including a plurality of clocks based on an external synchronization signal input thereto, the external synchronization signal having a frequency that increases by a multiple; and

generate a scan pulse signal to scan the display panel based on the generated internal horizontal synchronization signal,

wherein the internal horizontal synchronization signal includes a first clock and a second clock arranged sequentially, and

wherein a temporal interval between a falling edge and a rising edge of the scan pulse signal is equal to a temporal interval between a falling edge of the first clock and a falling edge of the second clock.

2 . The display apparatus of claim 1 , wherein the controller comprises:

a timing controller configured to generate the internal horizontal synchronization signal based on the external synchronization signal and to generate the scan pulse signal configured to drive the display panel based on the generated internal horizontal synchronization signal; and

a data driver configured to convert an image data transmitted from the timing controller into a data voltage and to supply the data voltage to the display panel.

3 . The display apparatus of claim 2 , wherein the timing controller is further configured to generate the internal horizontal synchronization signal having a frequency increased by the multiple based on the external synchronization signal having the frequency increased by the multiple.

4 . The display apparatus of claim 3 , wherein the multiple is 2,

wherein the timing controller is further configured to generate the internal horizontal synchronization signal so that after a voltage of the first clock of the internal horizontal synchronization signal falls from a first high voltage to a first low voltage, a first point at which a voltage of the second clock of the internal horizontal synchronization signal rises from a low voltage to a high voltage and a second point at which a voltage of the first clock of the internal horizontal synchronization signal rises from a low level to a high level correspond with each other.

5 . The display apparatus of claim 4 , wherein the timing controller is further configured to generate the internal horizontal synchronization signal so that after the voltage of the second clock of the internal horizontal synchronization signal falls from the high voltage to the low voltage, a third point at which a voltage of a third clock following the second clock of the internal horizontal synchronization signal rises from the low voltage to the high voltage and a fourth point at which a voltage of a second clock of the internal horizontal synchronization signal rises from the low level to the high level correspond with each other.

6 . The display apparatus of claim 5 , wherein the scan pulse signal is transmitted to a first scan pulse line, and

wherein the timing controller is further configured to generate the scan pulse signal such that when the voltage of the first clock of the internal horizontal synchronization signal falls from the high level to the low level, the scan pulse signal falls from a high voltage level to a low voltage level, and when the voltage of the second clock of the internal horizontal synchronization signal falls from the high level to the low level, the scan pulse signal rises from the low voltage level to the high voltage level.

7 . The display apparatus of claim 6 , wherein the timing controller is further configured to generate the scan pulse signal with a clock of a period of time after a voltage of the third clock of the internal horizontal synchronization signal changes from a high level to a low level, and the scan pulse signal with the clock of the period of time is transmitted to a second scan pulse line.

8 . The display apparatus of claim 7 , wherein the timing controller is further configured such that a voltage of the clock of the period of time changes from a low voltage to a high voltage after a voltage of a fourth clock of the internal horizontal synchronization signal changes from a high level to a low level.

9 . The display apparatus of claim 6 , wherein the scan pulse signal is generated based on a point at which the voltage of the first clock of the internal horizontal synchronization signal falls and a point at which the voltage of the second clock of the internal horizontal synchronization signal falls.

10 . The display apparatus of claim 3 , wherein the multiple is 4,

wherein the timing controller is further configured to generate the internal horizontal synchronization signal so that after a voltage of the second clock of the internal horizontal synchronization signal falls from a high voltage to a low voltage, a first point at which a voltage of the third clock of the internal horizontal synchronization signal rises from the low voltage to the high voltage and a second point at which a voltage of the first clock of the internal horizontal synchronization signal rises from a low level to a high level correspond with each other.

11 . The display apparatus of claim 10 , wherein the timing controller is further configured to generate the internal horizontal synchronization signal so that after the voltage of the third clock of the internal horizontal synchronization signal falls from the high voltage to the low voltage, a third point at which a voltage of a fourth clock of the internal horizontal synchronization signal rises from the low voltage to the high voltage and a fourth point at which a voltage of the second clock of the internal horizontal synchronization signal rises from the low level to the high level correspond with each other.

12 . The display apparatus of claim 11 , wherein the scan pulse signal is transmitted to a first scan pulse line,

wherein the timing controller is further configured to generate the scan pulse signal such that when the voltage of the first clock of the internal horizontal synchronization signal falls from the high level to the low level, the scan pulse signal falls from a high voltage level to a low voltage level, and when the voltage of the fourth clock of the internal horizontal synchronization signal falls from the high level to the low level, the scan pulse signal rises from the low voltage level to the high voltage level.

13 . The display apparatus of claim 12 , wherein the timing controller is further configured to generate the scan pulse signal with a clock of a period of time after a voltage of a fifth clock of the internal horizontal synchronization signal changes from a high level to a low level, and the scan pulse signal with the clock of the certain period of time is transmitted to a second scan pulse line.

14 . The display apparatus of claim 13 , wherein the timing controller is further configured such that a voltage of the clock of the period of time changes from a low voltage to a high voltage at the time that a voltage of an eighth clock of the internal horizontal synchronization signal changes from a high level to a low level.

15 . The display apparatus of claim 12 , wherein the scan pulse signal is generated based on a point at which the voltage of the first clock of the internal horizontal synchronization signal falls and a point at which the voltage of the fourth clock of the internal horizontal synchronization signal falls.

16 . The display apparatus of claim 3 , wherein the timing controller is further configured to generate the internal horizontal synchronization signal whose voltage changes from a low level to a high level at a point when a voltage of the input synchronization signal rises from a low level to a high level.

17 . The display apparatus of claim 16 , wherein the internal horizontal synchronization signal is obtained by delaying the external synchronization signal.

18 . The display apparatus of claim 2 , wherein the timing controller and the data driver are integrated with each other.

19 . The display apparatus of claim 1 , wherein the external synchronization signal is input from an external system to the controller.