Method and apparatus for matched buffer decompression
A circuit includes a first clock having a first clock output and a second clock having a second clock output. The circuit also includes a first buffer having a first buffer input, a second buffer input, and a first buffer output, the second buffer input coupled to the first clock output and a second buffer having a third buffer input, a fourth buffer input, and a second buffer output, the third buffer input coupled to the first buffer output and the fourth buffer input coupled to the second clock output. Additionally, the circuit includes a first element of data memory having a first data input and a first data output, the first data input coupled to the first buffer output and a second element of data memory having a second data input and a second data output, the second data input coupled to the second buffer output.
1 . A circuit comprising:
a first clock having a first clock output;
a second clock having a second clock output;
a first buffer having a first buffer input, a second buffer input, and a first buffer output, the second buffer input coupled to the first clock output;
a second buffer having a third buffer input, a fourth buffer input, and a second buffer output, the third buffer input coupled to the first buffer output and the fourth buffer input coupled to the second clock output;
a first element of data memory having a first data input and a first data output, the first data input coupled to the first buffer output; and
a second element of data memory having a second data input and a second data output, the second data input coupled to the second buffer output.
2 . The circuit of claim 1 , further comprising:
a third clock having a third clock output; and
a parallel register having a first register input, a second register input, and a third register input, the first register input coupled to the first buffer output, the second register input coupled to the second buffer output, and the third register input coupled to the third clock output.
3 . The circuit of claim 2 , wherein the parallel register is configured to load data from the first element of data memory and from the second element of data memory in response to receiving a clock signal at the third register input.
4 . The circuit of claim 2 , further comprising logic circuits coupled between the first buffer output and the first register input and between the second buffer output and the second register input.
5 . The circuit of claim 4 , wherein the logic circuits are configured to:
determine which data in the first element of data memory and the second element of data memory contains compressed bits; and
decompress the compressed bits.
6 . The circuit of claim 1 , further comprising a transceiver device having a transceiver output coupled to the first buffer input.
7 . The circuit of claim 1 , wherein the first clock is configured to produce a first clock signal at the first clock output at a first time, the second clock is configured to produce a second clock signal at the second clock output at a second time, the second time different than the first time, the first buffer is configured to:
receive input data at the first buffer input; and
in response to receiving the first clock signal, write a first portion of the input data to the first element of data memory and to produce a second portion of the input data at the first buffer output; and wherein the second buffer is configured to, in response to receiving the second clock signal write at least a third portion of the second portion of the input data to the second element of data memory.
8 . The circuit of claim 1 , wherein the first clock and the second clock are configured to provide matching timing relationships in which a timing margin between data arrival and clock events at the first and second buffers is maintained within a threshold.
9 . The circuit of claim 8 , wherein the timing margin is approximately 1 nanosecond.
10 . The circuit of claim 1 , wherein physically positioned and routed on a semiconductor substrate to reduce timing skew.
11 . The circuit of claim 1 , wherein the circuit is implemented in a light modulator selected from the group consisting of: a digital micromirror device, a liquid crystal display, a liquid crystal on silicon device, and a phase light modulator.
12 . The circuit of claim 2 , wherein the circuit is implemented in a light modulator that includes a micromirror array, the circuit further comprising a display memory coupled to receive data from the parallel register, the display memory including an array of memory elements configured to control tilt or vertical displacement states of micromirrors of the micromirror array.
13 . The circuit of claim 12 , wherein the memory elements store configuration data for producing an image by the light modulator.
14 . The circuit of claim 4 , wherein the logic circuits are configured to identify compressed bits based on compressed control word (CCW) addressing bits in the compressed data.
15 . The circuit of claim 14 , wherein the compressed bits include uniform patterns of bits.
16 . The circuit of claim 1 , wherein the first and second clocks are configured to introduce timing skew that matches propagation delays through the first and second buffers.