Timing controller and working method thereof, display module, and electronic device

1 . A timing controller, configured to be used in a display panel and provide a timing control signal for driving the display panel, wherein the timing controller comprises:

a first non-volatile memory, configured to store software code for starting the timing controller;

a processor, configured to read the software code;

a demura correction circuit, configured to perform demura correction processing on a received first signal and output a processed first signal;

an anti-burn-in correction circuit, configured to perform anti-burn-in correction processing on a received second signal and output a processed second signal; and

a timing control circuit, configured to process a received third signal and output the timing control signal;

wherein the first non-volatile memory is further configured to:

store the timing control signal; and

buffer the timing control signal prior to the timing control signal being output to an external memory.

2 . The timing controller according to claim 1 ,

wherein the first non-volatile memory is further configured to store a firmware parameter representing identity information of the timing controller; and

wherein the processor is further configured to read and/or write the firmware parameter.

3 . The timing controller according to claim 1 ,

wherein the first non-volatile memory is further configured to store demura correction data; and

wherein the demura correction circuit is configured to perform demura correction processing on the received first signal based on the demura correction data read from the first non-volatile memory, and output the processed first signal.

4 . The timing controller according to claim 1 ,

wherein the first non-volatile memory is further configured to store anti-burn-in correction data; and

wherein the anti-burn-in correction circuit is configured to perform anti-burn-in correction processing on the received second signal based on the anti-burn-in correction data read from the first non-volatile memory, output the processed second signal, and write updated anti-burn-in correction data into the first non-volatile memory.

5 . The timing controller according to claim 1 , further comprising:

an overdrive circuit;

wherein the first non-volatile memory is further configured to store overdrive data; and

wherein the overdrive circuit is configured to write a received fourth signal into the first non-volatile memory, read the overdrive data, process the overdrive data, and output processed overdrive data.

6 . The timing controller according to claim 1 ,

wherein the first non-volatile memory is further configured to buffer video data input from the external memory.

7 . The timing controller according to claim 1 , wherein the first non-volatile memory and the processor are integrated into a same bare die.

8 . The timing controller according to claim 1 , further comprising:

an input/output interface coupled to the first non-volatile memory, wherein the input/output interface is configured to perform writing or reading with the external memory.

9 . The timing controller according to claim 1 , wherein the first non-volatile memory comprises one or more of a flash memory, a magnetoresistive random access memory, a resistive random access memory, a phase-change random access memory, or a ferroelectric memory.

10 . A display, comprising:

a display panel; and

a timing controller, wherein the timing controller is configured to provide a timing control signal for the display panel, and the timing controller comprises:

a first non-volatile memory, configured to store software code for starting the timing controller;

a processor, configured to read the software code;

a demura correction circuit, configured to perform demura correction processing on a received first signal and output a processed first signal;

an anti-burn-in correction circuit, configured to perform anti-burn-in correction processing on a received second signal and output a processed second signal; and

a timing control circuit, configured to process a received third signal and output the timing control signal;

wherein the first non-volatile memory is further configured to:

store the timing control signal; and

buffer the timing control signal prior to the timing control signal being output to an external memory.

11 . The display according to claim 10 , further comprising:

a second non-volatile memory, wherein the second non-volatile memory is coupled to the timing controller.

12 . An electronic device, comprising the display according to claim 10 and a housing, wherein the display is disposed in the housing.

13 . A timing controller assembly, configured to be used in a display panel and provide a timing control signal for driving the display panel, wherein the timing controller assembly comprises:

a timing controller; and

a third non-volatile memory, wherein the third non-volatile memory is disposed outside the timing controller;

wherein the timing controller comprises a processor and a first non-volatile memory, and the processor is directly coupled to the third non-volatile memory; and

wherein the first non-volatile memory is configured to:

store software code for starting the timing controller;

store the timing control signal; and

buffer the timing control signal prior to being output to an external memory.

14 . The timing controller assembly according to claim 13 , wherein the timing controller and the third non-volatile memory are two separate chips.

15 . The timing controller assembly according to claim 13 , wherein the timing controller further comprises a functional circuit, the functional circuit is configured to implement a function of the timing controller, and the functional circuit is directly coupled to the third non-volatile memory.