IP Library Granted Patent US 12706119
Granted Patent B1
US 12706119 · App. 19/064,052 · Granted Aug 11, 2026

Digital timing recovery in hard disk drive read channel for preamble reduction

Inventors: Nitin Nangare (Sunnyvale, CA); William J. Mitchem (Broomfield, CO)
Assignee: MARVELL ASIA PTE LTD
G11B20/10222G11B20/10046G11B20/10268
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Quick Facts
Patent No.
US 12706119
App. No.
19/064,052
Granted
Aug 11, 2026
Kind
B1
Abstract

A method of reading data from a rotating magnetic storage medium, having at least one read head, includes storing respective digitized data samples from each respective read head of the at least one read head in a respective timing buffer, determining a zero-phase start phase angle from a preamble of the digitized data samples, feeding forward the zero-phase start phase angle to an interpolator, selecting an interpolation filter based on the fed-forward zero-phase start phase angle, releasing the respective digitized data from the respective timing buffer after a duration sufficient for completion of the determining, the feeding forward and the selecting, and interpolating samples of the digitized data released from the respective timing buffer.

Claims (74)

1 . A method of reading data from a rotating magnetic storage medium having at least one read head, the method comprising:

storing respective digitized data samples from each respective read head of the at least one read head in a respective timing buffer, each of the respective digitized samples having a preamble length derived from a preamble tone;

determining a zero-phase start phase angle from a preamble of the digitized data samples;

feeding forward the zero-phase start phase angle to an interpolator;

selecting an interpolation filter based on the fed-forward zero-phase start phase angle; and

interpolating samples of the digitized data released from the respective timing buffer after a duration sufficient for completion of the determining, the feeding forward and the selecting.

2 . The method of claim 1 comprising determining the preamble length from a Discrete Fourier Transform of the preamble tone.

3 . The method of claim 2 wherein determining the preamble length from a Discrete Fourier Transform of the preamble tone comprises setting the preamble length to a length of the Discrete Fourier Transform of the preamble tone.

4 . The method of claim 1 wherein storing the respective digitized data samples, from each respective read head of the at least one read head in a respective timing buffer, comprises storing respective digitize samples having a preamble length derived from one of a 2 T preamble tone, a 3 T preamble tone, or a 4 T preamble tone.

5 . The method of reading data according to claim 1 , further comprising, where analog signals from each read head of the at least one read head are digitized at a clock rate that is oversampled relative to a bit rate of the data:

phase-rotating the digitized data prior to the determining, to account for the oversampled clock; and

releasing the data from the respective timing buffer, prior to the interpolating, after a duration sufficient for completion of the phase-rotating, the determining, the feeding forward and the selecting.

6 . The method of reading data according to claim 1 , further comprising:

equalizing the interpolated samples;

detecting data bits from the interpolated samples;

detecting timing error between the interpolated samples and the data bits; and

deriving a bit rate from the timing error;

wherein:

selecting the interpolation filter is based also on the bit rate.

7 . The method of reading data according to claim 1 , wherein determining a zero-phase start phase angle from the preamble of the digitized data comprises:

performing a Discrete Fourier Transform operation on the preamble of the digitized data;

deriving cosine values and sine values from the Discrete Fourier Transform operation; and

performing a CORDIC operation on the cosine values and the sine values to derive the zero-phase start phase angle.

8 . A storage device, comprising:

a rotating storage medium on which data is written, the data including user data preceded by a preamble occupying storage area whose size is derived from a preamble tone;

at least one read head;

a respective timing buffer configured to store respective digitized data samples from each respective read head of the at least one read head in a respective timing buffer, the respective digitize samples having the preamble with a preamble length derived from the preamble tone;

zero-phase start circuitry configured to determine a zero-phase start phase angle from the preamble of the digitized data samples;

interpolator circuitry, output of the zero-phase start circuitry being fed forward to the interpolator circuitry, the interpolator circuitry including an interpolation filter configured to be selected based on the zero-phase start phase angle; wherein:

the respective digitized data is released from the respective timing buffer after a duration sufficient for completion of operation of the zero-phase start circuitry and the interpolator circuitry; and

the interpolator circuitry is configured to interpolate samples of the digitized data released from the respective timing buffer.

9 . The storage device of claim 8 further comprising Discrete Fourier Transform circuitry, the size of the storage area being determined from a Discrete Fourier Transform of the preamble tone.

10 . The storage device of claim 9 wherein the Discrete Fourier Transform circuitry sets the size of the storage area to a length of the Discrete Fourier Transform of the preamble tone.

11 . The storage device of claim 10 wherein the Discrete Fourier Transform circuitry derives the size of the storage area from one of a 2 T preamble tone, a 3 T preamble tone, or a 4 T preamble tone.

12 . The storage device of claim 9 , wherein the zero-phase start circuitry comprises:

cosine accumulator circuitry configured to derive cosine values from output of the Discrete Fourier Transform circuitry;

sine accumulator circuitry configured to derive sine values from output of the Discrete Fourier Transform circuitry; and

CORDIC circuitry configured to operate on the cosine values and the sine values to derive the zero-phase start phase angle.

13 . The storage device of claim 8 , further comprising:

a respective analog-to-digital converter configured to digitize analog signals from a respective read head of the at least one read head, each respective analog-to-digital converter clocked by a clock that is oversampled relative to a bit rate of the data; and

phase-rotation circuitry configured to phase-rotate the digitized data prior to input to the zero-phase start circuitry, to account for the oversampled clock;

wherein:

the duration is further sufficient to account for completion of the phase-rotating.

14 . The storage device of claim 8 , further comprising:

equalization circuitry configured to filter the interpolated samples;

a data detector configured to detect data bits from the interpolated samples;

error-detecting circuitry configured to detect timing error between the interpolated samples and the data bits; and

a timing loop configured to derive a bit rate from the timing error; wherein:

the interpolator circuitry is configured to select an interpolation filter based on the bit rate.

15 . A storage device, comprising:

rotating storage means on which data is written, the data including user data preceded by a preamble occupying a storage area having a size derived from a preamble tone;

at least one read head means;

a respective timing buffer means configured to store respective digitized data samples from each respective read head of the at least one read head in a respective timing buffer, the respective digitize samples having the preamble with a preamble length derived from the preamble tone;

zero-phase start means configured to determine a zero-phase start phase angle from the preamble of the digitized data samples;

interpolator means, output of the zero-phase start means being fed forward to the interpolator means, the interpolator means including interpolation filter means configured to be selected based on the zero-phase start phase angle; wherein:

the respective digitized data is released from the respective timing buffer means after a duration sufficient for completion of operation of the zero-phase start means and the interpolator means; and

the interpolator means is configured to interpolate samples of the digitized data released from the respective timing buffer means.

16 . The storage device of claim 15 further comprising Discrete Fourier Transform means, the size of the storage area being determined from a Discrete Fourier Transform of the preamble tone.

17 . The storage device of claim 16 wherein the Discrete Fourier Transform means sets the size of the storage area to a length of the Discrete Fourier Transform of the preamble tone.

18 . The storage device of claim 17 wherein the Discrete Fourier Transform means derives the size of the storage area from one of a 2 T preamble tone, a 3 T preamble tone, or a 4 T preamble tone.

19 . The storage device of claim 16 , wherein the zero-phase start means comprises:

cosine accumulator means configured to derive cosine values from output of the Discrete Fourier Transform means;

sine accumulator means configured to derive sine values from output of the Discrete Fourier Transform means; and

CORDIC means configured to operate on the cosine values and the sine values to derive the zero-phase start phase angle.

20 . The storage device of claim 15 , further comprising:

a respective analog-to-digital converter means configured to digitize analog signals from a respective read head means of the at least one read head means, each respective analog-to-digital converter means clocked by clock means that is oversampled relative to a bit rate of the data; and

phase-rotation means configured to phase-rotate the digitized data prior to input to the zero-phase start means, to account for the oversampled clock means; wherein:

the duration is further sufficient to account for completion of the phase-rotating.

21 . The storage device of claim 15 , further comprising:

equalization means configured to filter the interpolated samples;

data detector means configured to detect data bits from the interpolated samples;

error-detecting means configured to detect timing error between the interpolated samples and the data bits; and

timing loop means configured to derive a bit rate from the timing error; wherein:

the interpolator means is configured to select an interpolation filter based on the bit rate.