Semiconductor device structure
A semiconductor device structure includes a silicon substrate, a transistor, and an interconnection. The silicon substrate has a silicon surface. The transistor includes a gate structure, a first conductive region, a second conductive region, and a channel under the silicon surface. The interconnection is extended beyond the transistor and coupled to the first conductive region of the transistor. The interconnection is disposed under the silicon surface and isolated from the silicon substrate by an isolation region.
1 . A method forming a semiconductor structure comprising:
preparing a semiconductor substrate with an original surface;
based on the semiconductor substrate, forming a set of active regions and forming a shallow trench isolation region between two adjacent active regions of the set of active regions;
forming asymmetrical spacers within the shallow trench isolation region between the two adjacent active regions, wherein a first spacer of the asymmetrical spacers is an oxide spacer covering a sidewall of a first active region of the two adjacent active regions, and a second spacer of the asymmetrical spacers is deposited within a narrow slot which reveal a sidewall of a second active region of the two adjacent active regions; and
forming a first interconnection layer between the asymmetrical spacers; wherein the first interconnection layer is within the shallow trench isolation region and under the original surface of the semiconductor substrate.
2 . The method of claim 1 , wherein the material of the first spacer is different from that of the second spacer.
3 . The method of claim 1 , wherein the second spacer is made of SiOCN.
4 . The method of claim 1 , further comprising:
forming a gate region of a transistor within the second active region and forming a second interconnection layer, wherein the gate region of the transistor is connected to the second interconnection layer; and
forming a connection plug in the second active region to electrically connect the first interconnection layer.
5 . The method of claim 4 , the step of forming the gate region of the transistor and the second interconnection layer comprising:
etching the second active region to create a concave therein;
depositing a high-k insulator layer in the concave; and
depositing a first conductive material to form the gate region of the transistor and the second interconnection.
6 . The method of claim 4 , the step of forming the connection plug comprising:
etching the second active region to create a hole and forming a dielectric layer in the hole;
based on the hole, removing the second spacer to reveal a sidewall of the first interconnection layer; and
depositing a second conductive material in the hole to contact the sidewall of the first interconnection layer.
7 . The method of claim 4 , wherein the semiconductor structure is a DRAM cell, the first interconnection layer is a bit line, the transistor is an access transistor of a DRAM cell, and the second interconnection layer is a word line.
8 . The method of claim 1 , the step of forming the asymmetrical spacers comprising:
forming the oxide spacer to cover the sidewall of the first active region, and forming a temporary oxide spacer to cover the second active region;
depositing a sacrificial layer over the shallow trench isolation region and covering the oxide spacer and the temporary oxide spacer;
forming the narrow slot by removing a first portion of the sacrificial layer and the temporary oxide spacer to reveal the sidewall of the second active region; and
depositing the second spacer within the narrow slot to cover the sidewall of the second active region.
9 . The method of claim 8 , wherein the narrow slot is fully occupied by the second spacer.
10 . The method of claim 8 , the step of forming the narrow slot comprising:
forming a patterned photo-resistance layer to reveal the first portion of the sacrificial layer; and
removing the first portion of the sacrificial layer and the temporary oxide spacer covered by the first portion of the sacrificial layer to form the narrow slot.
11 . The method of claim 8 , wherein a width of the narrow slot is 2~5 nm.