Semiconductor apparatus, memory, and electronic device

1 . A semiconductor apparatus, comprising:

at least two chips comprising a first chip and a second chip, each of the chips comprising:

a fuse circuit, configured to generate a first signal and a second signal through fuse burning, and output the first signal and the second signal;

an external pad, configured to receive a third signal input to the chip; and

a control circuit, connected to the external pad and the fuse circuit, the control circuit being configured to determine, based on the first signal, the second signal, and the third signal, a sequence of executing a command by the chip in which the control circuit is located in at least two chips.

2 . The semiconductor apparatus according to claim 1 , wherein the control circuit comprises:

a master/slave determining circuit, configured to determine a master/slave type of the chip based on the first signal, the second signal, and the third signal, and output a master/slave determining signal; and

an arbiter circuit, connected to the master/slave determining circuit, the arbiter circuit being configured to determine, based on the master/slave determining signal, the sequence of executing the command by the chip in which the arbiter circuit is located in the at least two chips.

3 . The semiconductor apparatus according to claim 2 , wherein the master/slave determining circuit comprises a selection circuit, configured to output the second signal or a fourth signal at a level opposite to that of the third signal as the master/slave determining signal based on the first signal.

4 . The semiconductor apparatus according to claim 3 , wherein a first output end of the fuse circuit is configured to output the first signal, a second output end of the fuse circuit is configured to output the second signal, and the selection circuit comprises:

a first inverter, an input end of the first inverter being connected to the first output end of the fuse circuit;

a first NAND gate, a first input end of the first NAND gate being connected to the second output end of the fuse circuit, and a second input end of the first NAND gate being connected to an output end of the first inverter;

a second inverter, an input end of the second inverter being connected to an output end of the first NAND gate;

a third inverter, connected to the external pad and configured to output the fourth signal at the level opposite to that of the third signal;

a second NAND gate, a first input end of the second NAND gate being connected to the first output end of the fuse circuit, and a second input end of the second NAND gate being connected to an output end of the third inverter;

a fourth inverter, an input end of the fourth inverter being connected to an output end of the second NAND gate;

a first NOR gate, a first input end of the first NOR gate being connected to an output end of the second inverter, and a second input end of the first NOR gate being connected to an output end of the fourth inverter; and

a fifth inverter, an input end of the fifth inverter being connected to an output end of the first NOR gate, and an output end of the fifth inverter being configured to output the master/slave determining signal.

5 . The semiconductor apparatus according to claim 2 , wherein the semiconductor apparatus further comprises a first calibration resistor, both the first chip and the second chip are coupled to the first calibration resistor, and the first chip and the second chip are configured to perform a resistance calibration operation through the first calibration resistor.

6 . The semiconductor apparatus according to claim 5 , wherein

the arbiter circuit determines that the chip in which the arbiter circuit is located is the first one performing the resistance calibration operation when the master/slave determining circuit determines that the chip in which the master/slave determining circuit is located is a master chip and outputs the master/slave determining signal at a first level; or

the arbiter circuit determines that the chip in which the arbiter circuit is located is the second one performing the resistance calibration operation when the master/slave determining circuit determines that the chip in which the master/slave determining circuit is located is a slave chip and outputs the master/slave determining signal at a second level.

7 . The semiconductor apparatus according to claim 5 , wherein the semiconductor apparatus further comprises:

a substrate, a third chip, and a fourth chip; the first chip and the second chip are located on a same plane of the substrate, the third chip is stacked on the first chip, and the fourth chip is stacked on the second chip;

each of the chips comprises a first calibration pin and a second calibration pin; the first calibration pin is configured to output a calibration complete signal when the chip completes the resistance calibration operation, and the second calibration pin is configured to receive, when another chip completes the resistance calibration operation, the calibration complete signal output by the another chip;

the first calibration pin of the first chip is connected to the second calibration pin of the second chip, and the second calibration pin of the first chip is connected to the first calibration pin of the second chip; and

the first calibration pin of the third chip is connected to the second calibration pin of the fourth chip, and the second calibration pin of the third chip is connected to the first calibration pin of the fourth chip.

8 . The semiconductor apparatus according to claim 7 , wherein the semiconductor apparatus further comprises a second calibration resistor, both the third chip and the fourth chip are coupled to the second calibration resistor, and the third chip and the fourth chip are configured to perform the resistance calibration operation through the second calibration resistor.

9 . The semiconductor apparatus according to claim 7 , wherein the semiconductor apparatus further comprises:

a fifth chip, a sixth chip, and a third calibration resistor; the fifth chip is stacked on the third chip, and the sixth chip is stacked on the fourth chip;

all of the first chip, the second chip, the third chip, and the fourth chip are coupled to the first calibration resistor; both the fifth chip and the sixth chip are coupled to the third calibration resistor; and

the first chip, the second chip, the third chip, and the fourth chip are configured to perform the resistance calibration operation through the first calibration resistor; and the fifth chip and the sixth chip are configured to perform the resistance calibration operation through the third calibration resistor.

10 . The semiconductor apparatus according to claim 9 , wherein the fuse circuit is further configured to generate a fifth signal through fuse burning, and output the fifth signal; and

the arbiter circuit is further connected to the fuse circuit, and the arbiter circuit is further configured to determine, based on the master/slave determining signal and the fifth signal, a sequence of executing the command by the chip in which the arbiter circuit is located in a plurality of chips.

11 . The semiconductor apparatus according to claim 10 , wherein

the arbiter circuit determines that the chip in which the arbiter circuit is located is the first one performing the resistance calibration operation when the master/slave determining signal is at a first level and the fifth signal is at the first level;

the arbiter circuit determines that the chip in which the arbiter circuit is located is the second one performing the resistance calibration operation when the master/slave determining signal is at a first level and the fifth signal is at a second level;

the arbiter circuit determines that the chip in which the arbiter circuit is located is the third one performing the resistance calibration operation when the master/slave determining signal is at a second level and the fifth signal is at a first level; or

the arbiter circuit determines that the chip in which the arbiter circuit is located is the fourth one performing the resistance calibration operation when the master/slave determining signal is at a second level and the fifth signal is at the second level.

12 . The semiconductor apparatus according to claim 2 , wherein the fuse circuit is further configured to generate a sixth signal through fuse burning, and output the sixth signal; and

the arbiter circuit is further connected to the fuse circuit, and the fuse circuit is further configured to enable or disable the arbiter circuit through the sixth signal.

13 . The semiconductor apparatus according to claim 1 , wherein the fuse circuit is further configured to adjust, through the first signal, a pin order of a plurality of command address signals input to the chip.

14 . A memory, comprising the semiconductor apparatus according to claim 1 .

15 . An electronic device, comprising the semiconductor apparatus according to claim 1 .