Staircase bridge structures for word line contacts in three-dimensional memory
Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, the 3D memory device includes a film stack having a plurality of conductive and dielectric layer pairs vertically stacked on a substrate. Each conductive and dielectric layer pair includes a dielectric layer and a conductive layer. The 3D memory device also includes a staircase region having a first and a second staircase structure formed in the film stack, where the first and second staircase structures each extends laterally in a first direction and includes the plurality of conductive and dielectric layer pairs. The staircase region further includes a staircase bridge connecting the first and second staircase structures.
1 . A semiconductor device, comprising:
a channel structure region and a staircase region arranged at a side of the channel structure region in a first direction;
a stack, comprising a first top select gate (TSG) and a second top select gate-TSG arranged in the first direction;
slit structures extending through the stack and extending in the first direction across the channel structure region and the staircase region;
a TSG cut structure extending through an upper portion of the stack and extending in the first direction, wherein the TSG cut structure is between adjacent slit structures in a second direction perpendicular to the first direction; and
a bridge structure extending in the first direction and connecting the first and second top select gates the bridge structure comprises a width in the second direction smaller than a distance between the adjacent slit structures.
2 . The semiconductor device of claim 1 , wherein the width of the bridge structure is smaller than a twice distance between the slit structures and the TSG cut structure adjacent to the slit structures in the second direction.
3 . The semiconductor device of claim 1 , further comprising bottom select gate (BSG) cut structures extending vertically through a bottom portion of the stack and extending in the first direction.
4 . The semiconductor device of claim 3 , wherein the width of the bridge structure is smaller than a distance between adjacent BSG cut structures of the BSG cut structures in the second direction.
5 . The semiconductor device of claim 1 , further comprising a first staircase structure and a second staircase structure extending in the stack in the first direction, wherein the bridge structure connects the first and second staircase structures.
6 . The semiconductor device of claim 5 , wherein the width of the bridge structure in the second direction is smaller than a width of the first and second staircase structures in the second direction.
7 . The semiconductor device of claim 1 , wherein, in the first direction, an upper portion of the bridge structure is longer than a lower portion of the bridge structure.
8 . The semiconductor device of claim 5 , further comprising contact structures, wherein the first and second staircase structures comprise pairs of conductive layers and dielectric layers, and the contact structures connect with the conductive layers of the first and second staircase structures.
9 . The semiconductor device of claim 8 , wherein
a first subset of the contact structures is on the conductive layers of the first staircase structure; and
a second subset of the contact structures is on the conductive layers of the second staircase structure, wherein the second subset of the contact structures is different from the first subset of the contact structures.
10 . The semiconductor device of claim 1 , wherein the stack further comprises conductive and dielectric layer pairs, each conductive and dielectric layer pair comprises a dielectric layer and a conductive layer.
11 . A semiconductor device, comprising:
a channel structure region and a staircase region arranged at a side of the channel structure region in a first direction;
a stack, comprising a first top select gate (TSG) and a second top select gate TSG arranged in the first direction and extending through an upper portion of the stack;
slit structures extending through the stack and extending in the first direction across the channel structure region and the staircase region, wherein the first and second TSGs are arranged between adjacent slit structures in a second direction perpendicular to the first direction;
a top select gate cut structure extending through the upper portion of the stack and extending in the first direction;
a first staircase structure in the stack;
a second staircase structure in the stack, wherein the first and second staircase structures each extends in the first direction; and
a bridge structure extending in the first direction and connecting the first and second staircase structures, wherein the bridge structure connects the first and second TSGs, and the bridge structure comprises a width in the second direction less than a total width of the first staircase structure and the second staircase structure in the second direction.
12 . The semiconductor device of claim 11 , further comprising bottom select gate (BSG) cut structures extending vertically through a bottom portion of the stack and extending in the first direction, wherein the bridge structure comprises the width in the second direction smaller than a distance between adjacent slit structures of the slit structures.