Memory and operation method thereof, and memory system
Examples of the present disclosure disclose a memory and an operation method thereof, and a memory system. The memory includes: a memory cell array including a plurality of memory cells; bit lines coupled to the plurality of memory cells; a plurality of word lines coupled to the plurality of memory cells; and a peripheral circuit coupled to the bit lines and the word lines. The peripheral circuit is configured to apply, at a first time period, a first voltage to a selected word line in the plurality of word lines to turn on a cell transistor of a memory cell coupled to the selected word line, and apply, at the first time period, a second voltage to at least one dummy word line in the plurality of word lines to turn on a cell transistor of a memory cell coupled to the at least one dummy word line.
1 . A memory, comprising:
a memory cell array comprising a plurality of blocks, each comprising a plurality of memory cells, wherein the plurality of blocks comprise a first block and a second block;
bit lines coupled to the plurality of memory cells, wherein a bit line for the first block and a bit line for the second block are connected to a same sense amplifier;
a plurality of word lines coupled to the plurality of memory cells; and
a peripheral circuit coupled to the bit lines and the word lines, and configured to:
apply, at a first time period, a first voltage to a selected word line in the plurality of word lines to turn on a cell transistor of a memory cell coupled to the selected word line;
apply, at the first time period, a second voltage to at least one dummy word line in the plurality of word lines to turn on a cell transistor of a memory cell coupled to the at least one dummy word line; and
while applying the second voltage to a first dummy word line in the first block apply the second voltage to a second dummy word line in the second block.
2 . The memory of claim 1 , wherein at the first time period, a cell capacitor of the memory cell coupled to the selected word line shares charges with the bit line.
3 . The memory of claim 2 , wherein the peripheral circuit is configured to:
at a second time period before the first time period, apply a pre-charging voltage to the bit line, and apply the second voltage to the at least one dummy word line.
4 . The memory of claim 3 , wherein the peripheral circuit is further configured to:
at a third time period after the second time period, amplify a voltage of the bit line that has been subjected to charge sharing;
apply the pre-charging voltage to the bit line at a fourth time period after the third time period; and
apply the second voltage to the at least one dummy word line at the third time period and the fourth time period.
5 . The memory of claim 4 , wherein a phase for a read operation on the memory cell coupled to the selected word line comprises the second time period, the first time period, the third time period, and the fourth time period; and
the peripheral circuit is further configured to:
apply the second voltage to the at least one dummy word line at another time period, wherein the other time period comprises a time period between an end moment of the fourth time period and a start moment of a second time period for a next read operation phase.
6 . The memory of claim 1 , wherein the peripheral circuit is configured to:
acquire an activated row address;
determine a first dummy row address in the first block and a second dummy row address in the second block according to the activated row address;
determine the first dummy word line and the second dummy word line based on the first dummy row address and the second dummy row address; and
determine the selected word line based on the activated row address.
7 . The memory of claim 1 , wherein the second voltage is less than the first voltage.
8 . The memory of claim 1 , wherein the word lines comprise the dummy word lines and normal word lines, and the selected word line is any one of the normal word lines; and
the dummy word lines are located on two sides of a plurality of the normal word lines; or the dummy word lines are located between any two adjacent normal word lines.
9 . A memory system, comprising:
one or more memories, comprising:
a memory cell array comprising a plurality of blocks, each comprising a plurality of memory cells, wherein the plurality of blocks comprise a first block and a second block;
bit lines coupled to the plurality of memory cells, wherein a bit line for the first block and a bit line for the second block are connected to a same sense amplifier;
a plurality of word lines coupled to the plurality of memory cells; and
a peripheral circuit coupled to the bit lines and the word lines, and configured to:
apply, at a first time period, a first voltage to a selected word line in the plurality of word lines to turn on a cell transistor of a memory cell coupled to the selected word line;
apply, at the first time period, a second voltage to at least one dummy word line in the plurality of word lines to turn on a cell transistor of a memory cell coupled to the at least one dummy word line; and
while applying the second voltage to a first dummy word line in the first block apply the second voltage to a second dummy word line in the second block; and
a memory controller coupled to the memories and configured to control the memories.
10 . The memory of claim 9 , wherein at the first time period, a cell capacitor of the memory cell coupled to the selected word line shares charges with the bit line.
11 . The memory of claim 10 , wherein the peripheral circuit is configured to:
at a second time period before the first time period, apply a pre-charging voltage to the bit line, and apply the second voltage to the at least one dummy word line.
12 . The memory of claim 11 , wherein the peripheral circuit is further configured to:
at a third time period after the second time period, amplify a voltage of the bit line that has been subjected to charge sharing;
apply the pre-charging voltage to the bit line at a fourth time period after the third time period; and
apply the second voltage to the at least one dummy word line at the third time period and the fourth time period.
13 . The memory of claim 12 , wherein a phase for a read operation on the memory cell coupled to the selected word line comprises the second time period, the first time period, the third time period, and the fourth time period; and
the peripheral circuit is further configured to:
apply the second voltage to the at least one dummy word line at another time period, wherein the other time period comprises a time period between an end moment of the fourth time period and a start moment of a second time period for a next read operation phase.
14 . An operation method of a memory, wherein the memory comprises a memory cell array, the memory cell array comprises a plurality of memory cells, and bit lines and a plurality of word lines are coupled to the plurality of memory cells, the memory cell array comprises a plurality of blocks each comprising the plurality of memory cells, the plurality of blocks comprise a first block and a second block, and a bit line for the first block and a bit line for the second block are connected to a same sense amplifier;
wherein the operation method comprises:
applying, at a first time period, a first voltage to a selected word line in the plurality of word lines to turn on a cell transistor of a memory cell coupled to the selected word line;
applying, at the first time period, a second voltage to at least one dummy word line in the plurality of word lines to turn on a cell transistor of a memory cell coupled to the at least one dummy word line; and
while applying the second voltage to a first dummy word line in the first block, apply the second voltage to a second dummy word line in the second block.
15 . The operation method of a memory of claim 14 , wherein at the first time period, charge sharing is performed between a cell capacitor of the memory cell coupled to the selected word line and the bit line.
16 . The operation method of a memory of claim 15 , further comprising:
at a second time period before the first time period, applying a pre-charging voltage to the bit line, and applying the second voltage to the at least one dummy word line.
17 . The operation method of a memory of claim 16 , further comprising:
at a third time period after the second time period, amplifying a voltage of the bit line that has been subjected to charge sharing;
applying the pre-charging voltage to the bit line at a fourth time period after the third time period; and
applying the second voltage to the at least one dummy word line at the third time period and the fourth time period.
18 . The operation method of a memory of claim 17 , wherein a phase for a read operation on the memory cell coupled to the selected word line comprises the second time period, the first time period, the third time period, and the fourth time period; and
the operation method further comprises:
applying the second voltage to the at least one dummy word line at another time period, wherein the other time period comprises a time period between an end moment of the fourth time period and a start moment of a second time period for a next read operation phase.
19 . The operation method of a memory of claim 18 , further comprising:
acquiring an activated row address;
determining, according to the activated row address, a first dummy row address in the first block and a second dummy row address in the second block;
determining the first dummy word line and the second dummy word line based on the first dummy row address and the second dummy row address; and
determining the selected word line based on the activated row address.
20 . The operation method of a memory of claim 14 , wherein the second voltage is less than the first voltage.