Fast look neighbor ahead for data recovery
A storage device is disclosed. The storage device is configured to: determine data states for a first set of memory cells of a first neighboring word line of the and a second set of memory cells of a second neighboring word line, the first and the second neighboring word lines being adjacent to a selected word line; identify a zone of a plurality of zones for each data state combination of the data states, each data state combination comprising a data state of a memory cell of the first set of memory cells and a data state of a memory cell of the second set of memory cells, each zone of the plurality of zones corresponding to a bit line clamping voltage; and perform a read operation on the selected word line including applying each bit line clamping voltage corresponding to any zones identified.
1 . A storage device, comprising:
a non-volatile memory including control circuitry and an array of memory cells formed using a set of word lines and a set of bit lines; and
a controller, coupled to the non-volatile memory, configured to:
determine data states for a first set of memory cells of a first word line of the set of word lines and a second set of memory cells of a second word line of the set of word lines, each of the data states being any of a plurality of data states that the first set and second set of memory cells are configured to store, the first and the second word lines being adjacent to a selected word line of the set of word lines, wherein determining data states for the first set of memory cells of the first word line and the second set of memory cells of the second word line includes performing a read operation with dual wordline current sensing;
identify a zone of a plurality of zones for each data state combination of the data states, each data state combination comprising a data state of a memory cell of the first set of memory cells and a data state of a memory cell of the second set of memory cells, the memory cell of the first set of memory cells and the memory cell of the second set of memory cells being adjacent to a memory cell of a third set of memory cells of the selected word line, and wherein each zone of the plurality of zones corresponds to a bit line clamping voltage; and
perform a read operation on the selected word line including applying each bit line clamping voltage corresponding to any zones of the plurality of zones identified for the third set of memory cells of the selected word line.
2 . The storage device as set forth in claim 1 , wherein each data state combination of a first zone of the plurality of zones comprises a data state of a memory cell of the first set of memory cells from a first set of data states and a data state of a memory cell of the second set of memory cells from a second set of data states, wherein the first set of data states includes same data states as the second set of data states.
3 . The storage device as set forth in claim 1 , wherein apply each bit line clamping voltage includes:
applying a first bit line clamping voltage value for a first zone of the plurality of zones; and
applying a second bit line clamping voltage value for a second zone of the plurality of zones, wherein the first bit line clamping voltage value is different from the second bit line clamping voltage value.
4 . The storage device as set forth in claim 1 , wherein apply each bit line clamping voltage includes applying different bit line clamping voltage values for each zone of the plurality of zones identified for the third set of memory cells of the selected word line.
5 . The storage device as set forth in claim 1 , wherein zones of the plurality of zones with lower neighbor states will be applied with lower bit line clamping voltages than zones of the plurality of zones with higher neighbor states.
6 . The storage device as set forth in claim 1 , wherein zones of the plurality of zones with higher neighbor states will be applied with higher bit line clamping voltages than zones of the plurality of zones with lower neighbor states.
7 . A method of operating a memory apparatus including a plurality of memory cells, the method comprising the steps of:
determining data states for a first set of memory cells of a first word line of the set of word lines and a second set of memory cells of a second word line of the set of word lines, each of the data states being any of a plurality of data states that the first set and second set of memory cells are configured to store, the first and the second word lines being adjacent to a selected word line of the set of word lines, wherein determining data states for the first set of memory cells of the first word line and the second set of memory cells of the second word line includes performing a read operation with dual wordline current sensing;
identifying a zone of a plurality of zones for each data state combination of the data states, each data state combination comprising a data state of a memory cell of the first set of memory cells and a data state of a memory cell of the second set of memory cells, the memory cell of the first set of memory cells and the memory cell of the second set of memory cells being adjacent to a memory cell of a third set of memory cells of the selected word line, and wherein each zone of the plurality of zones corresponds to a bit line clamping voltage; and
performing a read operation on the selected word line including applying each bit line clamping voltage corresponding to any zones of the plurality of zones identified for the third set of memory cells of the selected word line.
8 . The method as set forth in claim 7 , wherein each data state combination of a first zone of the plurality of zones comprises a data state of a memory cell of the first set of memory cells from a first set of data states and a data state of a memory cell of the second set of memory cells from a second set of data states, wherein the first set of data states includes same data states as the second set of data states.
9 . The method as set forth in claim 7 , wherein applying each bit line clamping voltage includes:
applying a first bit line clamping voltage value for a first zone of the plurality of zones; and
applying a second bit line clamping voltage value for a second zone of the plurality of zones, wherein the first bit line clamping voltage value is different from the second bit line clamping voltage value.
10 . The method as set forth in claim 7 , wherein applying each bit line clamping voltage includes applying different bit line clamping voltage values for each zone of the plurality of zones identified for the third set of memory cells of the selected word line.
11 . The method as set forth in claim 7 , wherein zones of the plurality of zones with lower neighbor states will be applied with lower bit line clamping voltages than zones of the plurality of zones with higher neighbor states.
12 . The method as set forth in claim 7 , wherein zones of the plurality of zones with higher neighbor states will be applied with higher bit line clamping voltages than zones of the plurality of zones with lower neighbor states.
13 . A controller in communication with a plurality of memory cells of a memory apparatus, the controller configured to:
determine data states for a first set of memory cells of a first word line of the set of word lines and a second set of memory cells of a second word line of the set of word lines, each of the data states being any of a plurality of data states that the first set and second set of memory cells are configured to store, the first and the second word lines being adjacent to a selected word line of the set of word lines, wherein determining data states for the first set of memory cells of the first word line and the second set of memory cells of the second word line includes performing a read operation with dual wordline current sensing;
identify a zone of a plurality of zones for each data state combination of the data states, each data state combination comprising a data state of a memory cell of the first set of memory cells and a data state of a memory cell of the second set of memory cells, the memory cell of the first set of memory cells and the memory cell of the second set of memory cells being adjacent to a memory cell of a third set of memory cells of the selected word line, and wherein each zone of the plurality of zones corresponds to a bit line clamping voltage; and
perform a read operation on the selected word line including applying each bit line clamping voltage corresponding to any zones of the plurality of zones identified for the third set of memory cells of the selected word line.
14 . The controller as set forth in claim 13 , wherein each data state combination of a first zone of the plurality of zones comprises a data state of a memory cell of the first set of memory cells from a first set of data states and a data state of a memory cell of the second set of memory cells from a second set of data states, wherein the first set of data states includes same data states as the second set of data states.
15 . The controller as set forth in claim 13 , wherein apply each bit line clamping voltage includes:
applying a first bit line clamping voltage value for a first zone of the plurality of zones; and
applying a second bit line clamping voltage value for a second zone of the plurality of zones, wherein the first bit line clamping voltage value is different from the second bit line clamping voltage value.
16 . The controller as set forth in claim 13 , wherein apply each bit line clamping voltage includes applying different bit line clamping voltage values for each zone of the plurality of zones identified for the third set of memory cells of the selected word line.
17 . The controller as set forth in claim 13 , wherein zones of the plurality of zones with lower neighbor states will be applied with lower bit line clamping voltages than zones of the plurality of zones with higher neighbor states.