Buried metal techniques for memory applications

1 . A device comprising:

multi-page memory having a first core array with bitcells accessible via first wordlines;

wordline drivers coupled to the bitcells in the first core array via the first wordlines; and

buried metal lines formed within a substrate, wherein:

the buried metal lines are used to couple the wordline drivers to the first wordlines,

the first wordlines are formed in frontside metal layers above the substrate,

the buried metal lines are formed within the substrate and extend laterally, parallel to the frontside metal layers, underneath the first wordlines, and

the buried metal lines are used to route first wordline signals from the wordline drivers to the bitcells in the first core array via the first wordlines.

2 . The device of claim 1 , wherein:

the bitcells and the wordline drivers are formed and disposed on the substrate above the buried metal lines formed within the substrate, and

the buried metal lines are formed within the substrate underneath the bitcells, the first wordlines, and the wordline drivers.

3 . The device of claim 1 , wherein:

the multi-page memory has a second core array with bitcells accessible via second wordlines, wherein the second wordlines are formed in frontside metal layers above the substrate,

the wordline drivers are coupled to the bitcells in the second core array via the second wordlines, and

the second wordlines are used to route second wordline signals from the wordline drivers to the bitcells in the second core array.

4 . The device of claim 3 , further comprising:

control circuitry that provides sense-amp enable signals to first input-output circuitry for the first core array and to second input-output circuitry for the second core array,

wherein the buried metal lines are used to couple the control circuitry to the first input-output circuitry, and frontside metal lines are used to couple the control circuitry to the second input-output circuitry, and

wherein the buried metal lines are used to route first sense-amp signals from the control circuitry to the first input-output circuitry, and the frontside metal lines are used to route second sense-amp signals from the control circuitry to the second input-output circuitry.

5 . The device of claim 3 , further comprising:

control circuitry that provides bitline precharge signals to first input-output circuitry for the first core array and to second input-output circuitry for the second core array,

wherein the buried metal lines are used to couple the control circuitry to the first input-output circuitry, and frontside metal lines are used to couple the control circuitry to the second input-output circuitry, and

wherein the buried metal lines are used to route first bitline precharge signals from the control circuitry to the first input-output circuitry, and the frontside metal lines are used to route second bitline precharge signals from the control circuitry to the second input-output circuitry.

6 . A device, comprising:

multi-page memory having a first core array with bitcells accessible via first wordlines and a second core array with bitcells accessible via second wordlines;

wordline drivers coupled to the bitcells in the first core array via the first wordlines and to the bitcells in the second core array via the second wordlines;

buried metal lines formed within a substrate, wherein the buried metal lines are used to couple the wordline drivers to the first wordlines; and

break-cell circuitry disposed between the first core array and the second core array,

wherein the break-cell circuitry receives a clock signal and an enable signal and then provides a wordline enable signal to the first core array or the second core array, and

wherein the buried metal lines are used to couple control circuitry to the break-cell circuitry, and the buried metal lines are used to route the wordline enable signal from the control circuitry to the break-cell circuitry.

7 . The device of claim 1 , wherein:

the multi-page memory has a third core array with bitcells that are accessible via third wordlines and a fourth core array with bitcells that are accessible via fourth wordlines, and

the buried metal lines are used to couple the wordline drivers to the fourth wordlines.

8 . The device of claim 7 , wherein:

the third wordlines are used to route third wordline signals from the wordline drivers to the bitcells in the third core array, and

the buried metal lines are used to route fourth wordline signals from the wordline drivers to the bitcells in the fourth core array via the fourth wordlines.

9 . The device of claim 7 , further comprising:

control circuitry that provides sense-amp enable signals to third input-output circuitry for the third core array and to fourth input-output circuitry for the fourth core array,

wherein frontside metal lines are used to couple the control circuitry to the third input-output circuitry, and the buried metal lines are used to couple the control circuitry to the fourth input-output circuitry, and

wherein the frontside metal lines are used to route third sense-amp signals from the control circuitry to the third input-output circuitry, and the buried metal lines are used to route fourth sense-amp signals from the control circuitry to the fourth input-output circuitry.

10 . The device of claim 7 , further comprising:

control circuitry that provides bitline precharge signals to third input-output circuitry for the third core array and to fourth input-output circuitry for the fourth core array,

wherein frontside metal lines are used to couple the control circuitry to the third input-output circuitry, and the buried metal lines are used to couple the control circuitry to the fourth input-output circuitry, and

wherein the frontside metal lines are used to route third bitline precharge signals from the control circuitry to the third input-output circuitry, and the buried metal lines are used to route fourth bitline precharge signals from the control circuitry to the fourth input-output circuitry.

11 . The device of claim 10 , further comprising:

break-cell circuitry disposed between the third core array and the fourth core array,

wherein the break-cell circuitry receives a clock signal and an enable signal and then provides a wordline enable signal to the third core array or the fourth core array, and

wherein the buried metal lines are used to couple the control circuitry to the break-cell circuitry, and the buried metal lines are used to route the wordline enable signal from the control circuitry to the break-cell circuitry.

12 . A device comprising:

multi-bank memory having a first core array with bitcells accessible via first wordlines and a second core array with bitcells accessible via second wordlines;

first wordline drivers coupled to the bitcells in the first core array via the first wordlines;

second wordline drivers coupled in series with the first wordline drivers, wherein the second wordline drivers are coupled to the bitcells in the second core array via the second wordlines; and

buried metal lines formed within a substrate, wherein the buried metal lines are used to couple third wordlines in parallel to the first wordlines, and wherein the buried metal lines are used to couple fourth wordlines in parallel to the second wordlines.

13 . The device of claim 12 , wherein:

the bitcells, the first wordline drivers and the second wordline drivers are formed and disposed on the substrate above the buried metal lines formed within the substrate,

the first wordlines and the second wordlines are formed in frontside metal layers above the substrate, and

the buried metal lines are formed within the substrate underneath the bitcells, the first wordlines, the second wordlines, the first wordline drivers and the second wordline drivers.

14 . The device of claim 12 , wherein:

the first wordlines are used to route first wordline signals from the first wordline drivers to the bitcells in the first core array and to the second wordline drivers,

the buried metal lines are used to route the first wordline signals from the first wordline drivers to the second wordlines drivers,

the second wordlines are used to route second wordline signals from the second wordline drivers to the bitcells in the second core array, and

the buried metal lines are used to route the second wordline signals from the second wordline drivers to the bitcells in the second core array.

15 . The device of claim 12 , further comprising:

third wordline drivers coupled in parallel with the first wordline drivers; and

open-breaks formed in the first wordlines that decouple the first wordline drivers from the second wordline drivers.

16 . The device of claim 15 , wherein:

the first wordlines are used to route first wordline signals from the first wordline drivers to the bitcells in the first core array,

the buried metal lines are used to route the first wordline signals from the first wordline drivers to the second wordlines drivers,

the second wordlines are used to route second wordline signals from the second wordline drivers to the bitcells in the second core array, and

the buried metal lines are used to route the second wordline signals from the second wordline drivers to the bitcells in the second core array.

17 . The device of claim 1 , wherein the buried metal lines are coupled to the first wordlines by way of through-silicon vias.

18 . The device of claim 1 , wherein the buried metal lines are coupled to the wordline drivers by way of through-silicon vias.