Erase operation with electron injection for reduction of cell-to-cell interference in a memory sub-system

1 . A memory device comprising:

a memory array comprising a set of memory cells; and

control logic, operatively coupled with the memory array, to perform operations comprising:

causing, during execution of an erase operation to erase a memory block associated with a set of wordlines, a programming pulse to be applied to the set of wordlines, wherein the programming pulse causes a set of electrons to be injected into a first set of gate regions and a second set of gate regions;

executing, during the erase operation, a first erase sub-operation on a first subset of the set of wordlines to remove a first subset of the set of electrons from the first set of gate regions; and

executing, during the erase operation, a second erase sub-operation on a second subset of the set of wordlines to remove a second subset of the set of electrons from the second set of gate regions.

2 . The memory device of claim 1 , wherein the first erase sub-operation comprises a first erase cycle.

3 . The memory device of claim 2 , wherein the first erase cycle comprises a first set of one or more erase pulses.

4 . The memory device of claim 3 , wherein each of the first set of one or more erase pulses is followed by an erase verify operation.

5 . The memory device of claim 1 , the operations further comprising causing a high voltage level to be applied to the second subset of wordlines during the first erase sub-operation, wherein the high voltage level is greater than or equal to an erase voltage level of an erase pulse applied during the first erase sub-operation.

6 . The memory device of claim 1 , wherein, following the executing of the second erase sub-operation, a third subset of the set of electrons remain in a set of inter-cell regions of a charge trap layer.

7 . The memory device of claim 6 , the operations further comprising, following the executing of the second erase sub-operation, executing a programming operation to program the first subset of the set of electrons and the second subset of the set of electrons.

8 . A method comprising:

causing, during execution of an erase operation to erase a memory block associated with a set of wordlines of a memory device, a programming pulse to be applied to the set of wordlines, wherein the programming pulse causes a set of electrons to be injected into a first set of gate regions and a second set of gate regions;

executing, during the erase operation, a first erase sub-operation on a first subset of the set of wordlines to remove a first subset of the set of electrons from the first set of gate regions; and

executing, during the erase operation, a second erase sub-operation on a second subset of the set of wordlines to remove a second subset of the set of electrons from the second set of gate regions.

9 . The method of claim 8 , wherein the first erase sub-operation comprises a first erase cycle.

10 . The method of claim 9 , wherein the first erase cycle comprises a first set of one or more erase pulses.

11 . The method of claim 10 , wherein each of the first set of one or more erase pulses is followed by an erase verify operation.

12 . The method of claim 8 , further comprising causing a high voltage level to be applied to the second subset of wordlines during the first erase sub-operation, wherein the high voltage level is greater than or equal to an erase voltage level of an erase pulse applied during the first erase sub-operation.

13 . The method of claim 9 , wherein, following the executing of the second erase sub-operation, a third subset of the set of electrons remain in a set of inter-cell regions of a charge trap layer.

14 . The method of claim 13 , further comprising, following the executing of the second erase sub-operation, executing a programming operation to program the first subset of the set of electrons and the second subset of the set of electrons.

15 . A memory device comprising:

a memory array comprising a set of memory cells; and

control logic, operatively coupled with the memory array, to perform operations comprising:

causing, during execution of an erase operation, injection of a set of electrons into a charge trap (CT) layer of the memory device;

causing, by executing a first erase sub-operation of the erase operation, removal of a first subset of the set of electrons from the CT layer of the memory device; and

causing, by executing a second erase sub-operation of the erase operation, removal of a second subset of the set of electrons from the CT layer of the memory device.

16 . The memory device of claim 15 , wherein the first erase sub-operation is executed to remove the first subset of the set of electrons from a first subset of regions of the CT layer corresponding to a first subset of wordlines of the memory device.

17 . The memory device of claim 16 , wherein the second erase sub-operation is executed to remove the first subset of set of electrons from a second subset of regions of the CT layer corresponding to a second subset of wordlines of the memory device.

18 . The memory device of claim 17 , the operations further comprising:

causing, during the first erase sub-operation, a first voltage level to be applied to the second subset of wordlines; and

causing, during the first erase sub-operation, a ground voltage level to be applied to the first subset of wordlines.

19 . The memory device of claim 18 , the operations further comprising:

causing, during the second erase sub-operation, a second voltage level to be applied to the first subset of wordlines; and

causing, during the second erase sub-operation, the ground voltage level to be applied to the second subset of wordlines.

20 . The memory device of claim 15 , the operations further comprising executing a programming operation to program the set of memory cells.