Memristor-enabled programmable sensing and switching threshold adjustment

1 . A circuit comprising:

a first PMOS transistor having a source terminal coupled to a first node and a drain terminal coupled to a second node;

a first programmable memristor having a first terminal coupled to the first node and a second terminal adapted to receive a first voltage; and

a first select transistor having a first source/drain terminal coupled to the first node, a second drain/source terminal coupled to a third node adapted to receive a second voltage, and a gate terminal receiving a first select signal, wherein a resistance of the first programmable memristor is responsive to a difference between the first and second voltages thereby to change a pullup strength of the first PMOS transistor, wherein the resistance of the first programmable memristor increases if the first voltage is greater than the second voltage, and wherein the resistance of the first programmable memristor decreases if the second voltage is greater than the first voltage.

2 . The circuit of claim 1 further comprising:

a first NMOS transistor having a drain terminal coupled to a fourth node and a source terminal coupled to a fifth node;

a second programmable memristor having a first terminal coupled to the fifth node and a second terminal coupled to a third voltage; and

a second select transistor having a first source/drain terminal coupled to the fifth node, a second drain/source terminal coupled to a sixth node adapted to receive a fourth voltage, and a gate terminal receiving a second select signal, wherein a resistance of the second programmable memristor is responsive to a difference between the third and fourth voltages thereby to change a pulldown strength of the first NMOS transistor.

3 . W The circuit of claim 2 , wherein the second node is connected to the fourth node thus causing the first PMOS transistor and the first NMOS transistor to form an inverter.

4 . The circuit of claim 3 , wherein the third voltage is a ground voltage or a virtual ground voltage.

5 . The circuit of claim 1 , wherein the first select transistor is an NMOS transistor.

6 . The circuit of claim 1 further comprising:

a second PMOS transistor having a source terminal coupled to the drain terminal of the first PMOS transistor, and a drain terminal coupled to a fourth node.

7 . The circuit of claim 1 further comprising:

a second PMOS transistor having a source terminal coupled to a fourth node and a drain terminal coupled to the second node;

a second programmable memristor having a first terminal coupled to the fourth node and a second terminal adapted to receive the first voltage; and

a second select transistor having a source/drain terminal coupled to the fourth node, a drain/source terminal coupled to a fifth node adapted to receive the second voltage, and a gate terminal receiving a second select signal, wherein a resistance of the second programmable memristor is responsive to a difference between the first and second voltages thereby to change a pullup strength of the second PMOS transistor.

8 . The circuit of claim 1 further comprising:

a second PMOS transistor having a source terminal receiving the first voltage and a drain terminal coupled to the second node.

9 . The circuit of claim 1 further comprising:

a second select transistor adapted to supply the first voltage to the second terminal of the first programmable memristor in response to a signal applied to a gate terminal of the second select transistor.

10 . The circuit of claim 2 further comprising:

a second NMOS transistor having a source terminal coupled to the drain terminal of the first NMOS transistor;

a second PMOS transistor having a drain terminal coupled to a drain terminal of the second NMOS transistor, and a gate terminal coupled to a gate terminal of the second NMOS transistor;

a third programmable memristor coupled between a source terminal of the second PMOS transistor and a terminal supplying the first voltage;

a third NMOS transistor having a drain terminal coupled to the drain terminal of the first PMOS transistor, and a gate terminal coupled to a gate terminal of the first PMOS transistor;

a fourth NMOS transistor having a drain terminal coupled to a source terminal of the third NMOS transistor, and a gate terminal receiving a reference voltage;

a third programmable memristor coupled between a source terminal of the second PMOS transistor and a first supply terminal supplying the first voltage;

a fourth programmable memristor having a first terminal coupled to a source terminal of the fourth NMOS transistor;

a third PMOS transistor having a source terminal receiving the first voltage, a drain terminal coupled to a drain terminal of the second PMOS transistor, and a gate terminal receiving a clock signal;

a fourth PMOS transistor having a source terminal receiving the first voltage, a drain terminal coupled to the drain terminal of the first PMOS transistor, and a gate terminal receiving the clock signal; and

a fifth NMOS transistor having a drain terminal coupled to a second terminal of the fourth programmable memristor, a source terminal receiving the third voltage, and a gate terminal receiving the clock signal.

11 . A method comprising:

coupling a source terminal of a first PMOS transistor to a first node and a drain terminal of the first PMOS transistor to a second node;

coupling a first terminal of a first programmable memristor to the first node and a second terminal of the first programmable memristor to a first voltage;

coupling a first source/drain terminal of a first select transistor to the first node, a second drain/source terminal of the first select transistor to a third node adapted to receive a second voltage;

applying a first select signal to a gate terminal of the select transistor; and

passing a first current through the first programmable memristor via the first select transistor to change a resistance of the first programmable memristor thereby to change a pullup strength of the first PMOS transistor, wherein the resistance of the first programmable memristor increases if the first voltage is greater than the second voltage, and wherein the resistance of the first programmable memristor decreases if the second voltage is greater than the first voltage.

12 . The method of claim 11 further comprising:

forming a first NMOS transistor having a drain terminal coupled to a fourth node and a source terminal coupled to a fifth node;

forming a second programmable memristor having a first terminal coupled to the fifth node and a second terminal coupled to a third voltage;

forming a second select transistor having a first source/drain terminal coupled to the fifth node, a second drain/source terminal coupled to a sixth node adapted to receive a fourth voltage, and a gate terminal receiving a second select signal; and

passing a second current through the second programmable memristor via the select transistor to change a resistance of the second programmable memristor thereby to change a pulldown strength of the first NMOS transistor.

13 . The method of claim 12 further comprising:

connecting the second node to the fourth node to form an inverter between the first PMOS transistor and the first NMOS transistor.

14 . The method of claim 13 wherein the third voltage is a ground voltage or a virtual ground voltage.

15 . The method of claim 11 further comprising:

causing the first current to flow from the first terminal of the first programmable memristor to a fourth node supplying the first voltage.

16 . The method of claim 11 further comprising:

causing the first current to flow from a fourth node supplying the first voltage to the first terminal of the first programmable memristor.

17 . The method of claim 11 , wherein the first select transistor is an NMOS transistor.

18 . A system comprising:

a memory storing instructions; and

a processor, coupled with the memory and to execute the instructions, the instructions when executed cause the processor to form a circuit comprising:

a first PMOS transistor having a source terminal coupled to a first node and a drain terminal coupled to a second node;

a first programmable memristor having a first terminal coupled to the first node and a second terminal adapted to receive a first voltage; and

a first select transistor having a first source/drain terminal coupled to the first node, a second drain/source terminal coupled to a third node adapted to receive a second voltage, and a gate terminal receiving a first select signal, wherein a resistance of the first programmable memristor is responsive to a difference between the first and second voltages thereby to change a pullup strength of the first PMOS transistor, wherein the resistance of the first programmable memristor increases if the first voltage is greater than the second voltage, and wherein the resistance of the first programmable memristor decreases if the second voltage is greater than the first voltage.

19 . The system of claim 18 , wherein the circuit further comprises:

a first NMOS transistor having a drain terminal coupled to a fourth node and a source terminal coupled to a fifth node;

a second programmable memristor having a first terminal coupled to the fifth node and a second terminal coupled to a third voltage; and

a second select transistor having a first source/drain terminal coupled to the fifth node, a second drain/source terminal coupled to a sixth node adapted to receive a fourth voltage, and a gate terminal receiving a second select signal, wherein a resistance of the second programmable memristor is responsive to a difference between the third and fourth voltages thereby to change a pulldown strength of the first NMOS transistor.