Semiconductor device and electronic system
A semiconductor device includes a lower stepped connection part at a first vertical level on a substrate, an upper stepped connection part at a second vertical level higher than the first vertical level on the substrate, a lower insulating block contacting each of the plurality of lower conductive pad parts at the first vertical level, an upper insulating block contacting each of the plurality of upper conductive pad parts at the second vertical level, an intermediate insulating film between the lower insulating block and the upper insulating block at a third vertical level between the first and second vertical levels, and a first plug structure extending into the lower stepped connection part, the intermediate insulating film, and the upper insulating block in the vertical direction, wherein a width of the first plug structure in the horizontal direction is greatest at the third vertical level.
1 . A semiconductor device comprising:
a substrate;
a lower stepped connection part disposed at a first vertical level on the substrate and having a plurality of lower conductive pad parts;
an upper stepped connection part disposed at a second vertical level higher than the first vertical level on the substrate and having a plurality of upper conductive pad parts;
a lower insulating block in contact with each of the plurality of lower conductive pad parts at the first vertical level and covering the lower stepped connection part;
an upper insulating block in contact with each of the plurality of upper conductive pad parts at the second vertical level, the upper insulating block including a part covering the upper stepped connection part and a part covering the lower insulating block;
an intermediate insulating film arranged between the lower insulating block and the upper insulating block at a third vertical level between the first vertical level and the second vertical level; and
a first plug structure configured to penetrate the lower stepped connection part, the intermediate insulating film, and the upper insulating block in the vertical direction at a position horizontally spaced from the upper stepped connection part, the first plug structure in which a width in the horizontal direction is greatest at the third vertical level,
wherein the first plug structure comprises:
a lower plug portion at the first vertical level and including a portion penetrating the lower stepped connection part;
an upper plug portion disposed at the second vertical level and surrounded by the upper insulating block; and
a plug landing portion arranged between the lower plug portion and the upper plug portion at the third vertical level, wherein a horizontal width of the plug landing portion is variable in the vertical direction and the plug landing portion gradually decreases towards the lower plug portion and has an inverted trapezoidal cross section including a horizontal bottom portion that extends away from sidewalls of the lower plug portion,
wherein the first plug structure comprises a first memory cell contact configured to be electrically connectable to one lower conductive pad part selected from among the plurality of lower conductive pad parts,
wherein the semiconductor device further comprises a second memory cell contact configured to penetrate the upper stepped connection part in the vertical direction and configured to be electrically connectable to one upper conductive pad part selected from among the plurality of upper conductive pad parts,
wherein the first memory cell contact and the second memory cell contact are apart from each other in the horizontal direction,
wherein a first width of an uppermost surface of the first memory cell contact in the horizontal direction is greater than a second width of an uppermost surface of the second memory cell contact, and
wherein the first memory cell contact and the second memory cell contact have different greatest widths in the horizontal direction.
2 . The semiconductor device of claim 1 , wherein the plug landing portion arranged between the lower plug portion and the upper plug portion protrudes in the horizontal direction from a first sidewall of the lower plug portion and a second sidewall of the upper plug portion at the third vertical level.
3 . The semiconductor device of claim 1 , wherein the lower plug portion has an uppermost portion adjacent to a bottom surface of the plug landing portion, wherein the upper plug portion has a lowermost portion adjacent to an upper surface of the plug landing portion, and wherein a width of the lowermost portion of the upper plug portion in the horizontal direction is greater than a width of the uppermost portion of the lower plug portion.
4 . The semiconductor device of claim 1 , wherein the first plug structure comprises a through electrode configured to penetrate at least one lower conductive pad part selected from among the plurality of lower conductive pad parts in the vertical direction and configured not to be electrically connected to the plurality of lower conductive pad parts.
5 . The semiconductor device of claim 1 , further comprising a second plug structure penetrating the upper stepped connection part in the vertical direction,
wherein a first width of an uppermost surface of the first plug structure in the horizontal direction is greater than a second width of an uppermost surface of the second plug structure.
6 . The semiconductor device of claim 1 , further comprising a peripheral circuit structure comprising a lower substrate, a plurality of circuits between the lower substrate and the substrate, and a plurality of wiring layers connected to the plurality of circuits,
wherein the first plug structure extends to the peripheral circuit structure through the substrate and is connected to at least one wiring layer selected from among the plurality of wiring layers.
7 . A semiconductor device comprising:
a substrate including a memory cell region and a connection region;
a first stack disposed at a first vertical level on the substrate, the first stack including a lower stepped connection part having a plurality of lower gate lines overlapping each other in a vertical direction in the memory cell region and a plurality of lower conductive pad parts disposed in the connection region and integrally connected to the plurality of lower gate lines;
a second stack disposed at a second vertical level higher than the first vertical level on the substrate, the second stack including an upper stepped connection part having a plurality of upper gate lines overlapping each other in the vertical direction in the memory cell region and a plurality of upper conductive pad parts disposed in the connection region and integrally connected to the plurality of upper gate lines;
a lower insulating block configured to cover the lower stepped connection part at the first vertical level;
an upper insulating block configured to cover the upper stepped connection part and the lower insulating block at the second vertical level;
an intermediate insulating film arranged between the first stack and the second stack and between the lower insulating block and the upper insulating block at a third vertical level between the first vertical level and the second vertical level; and
a plug structure penetrating the lower stepped connection part, the intermediate insulating film, and the upper insulating block in the vertical direction at a location horizontally apart from the first stack in the connection region, the plug structure in which a width in the horizontal direction is greatest at the third vertical level,
wherein the plug structure comprises:
a lower plug portion at the first vertical level and including a portion penetrating the lower stepped connection part;
an upper plug portion disposed at the second vertical level and surrounded by the upper insulating block; and
a plug landing portion arranged between the lower plug portion and the upper plug portion at the third vertical level, wherein a horizontal width of the plug landing portion is variable in the vertical direction and the plug landing portion gradually decreases towards the lower plug portion and has a semicircular cross section,
wherein the plug structure comprises a first memory cell contact configured to be electrically connectable to one lower conductive pad part selected from among the plurality of lower conductive pad parts,
wherein the semiconductor device further comprises a second memory cell contact configured to penetrate the upper stepped connection part in the vertical direction and configured to be electrically connectable to one upper conductive pad part selected from among the plurality of upper conductive pad parts,
wherein the first memory cell contact and the second memory cell contact are apart from each other in the horizontal direction, and wherein a first width of an uppermost surface of the first memory cell contact in the horizontal direction is greater than a second width of an uppermost surface of the second memory cell contact, and
wherein the first memory cell contact and the second memory cell contact have different greatest widths in the horizontal direction.
8 . The semiconductor device of claim 7 , wherein the plug landing portion protrudes in the horizontal direction from a first sidewall of the lower plug portion and a second sidewall of the upper plug portion at the third vertical level, and
wherein a first width of an uppermost portion of the lower plug portion adjacent to a bottom surface of the plug landing portion in the horizontal direction is less than a second width of a lowermost portion of the upper plug portion adjacent to an upper surface of the plug landing portion.
9 . An electronic system comprising:
a main board;
a semiconductor device on the main board; and
a controller electrically connected to the semiconductor device on the main board,
wherein the semiconductor device comprises:
a substrate;
a lower stepped connection part disposed at a first vertical level on the substrate and having a plurality of lower conductive pad parts;
an upper stepped connection part disposed at a second vertical level higher than the first vertical level on the substrate and having a plurality of upper conductive pad parts;
a lower insulating block in contact with each of the plurality of lower conductive pad parts at the first vertical level and covering the lower stepped connection part;
an upper insulating block in contact with each of the plurality of upper conductive pad parts at the second vertical level, the upper insulating block including a part covering the upper stepped connection part and a part covering the lower insulating block; and
an intermediate insulating layer arranged between the lower insulating block and the upper insulating block at a third vertical level between the first vertical level and the second vertical level;
a plug structure configured to penetrate the lower stepped connection part, the intermediate insulating film, and the upper insulating block in the vertical direction at a position horizontally spaced from the upper stepped connection part, the plug structure in which a width in the horizontal direction is greatest at the third vertical level
wherein the plug structure comprises:
a lower plug portion at the first vertical level and including a portion penetrating the lower stepped connection part;
an upper plug portion disposed at the second vertical level and surrounded by the upper insulating block; and
a plug landing portion arranged between the lower plug portion and the upper plug portion at the third vertical level, wherein a horizontal width of the plug landing portion is variable in the vertical direction and the plug landing portion gradually decreases towards the lower plug portion and has a semicircular cross section,
wherein the plug structure comprises a first memory cell contact configured to be electrically connectable to one lower conductive pad part selected from among the plurality of lower conductive pad parts,
wherein the semiconductor device further comprises a second memory cell contact configured to penetrate the upper stepped connection part in the vertical direction and configured to be electrically connectable to one upper conductive pad part selected from among the plurality of upper conductive pad parts,
wherein the first memory cell contact and the second memory cell contact are apart from each other in the horizontal direction, and wherein a first width of an uppermost surface of the first memory cell contact in the horizontal direction is greater than a second width of an uppermost surface of the second memory cell contact, and
wherein the first memory cell contact and the second memory cell contact have different greatest widths in the horizontal direction.