Three-dimensional memory devices and fabricating methods thereof

1 . A memory device, comprising:

a first semiconductor structure, comprising:

a first transistor comprising a first gate dielectric layer;

a first semiconductor layer disposed on the first transistor;

an isolation structure vertically penetrating through the first semiconductor layer to electrically isolate a second transistor;

a first insulating layer disposed on the first transistor;

first interconnect structures disposed in the first insulating layer, wherein at least one of the first interconnect structures is electrically connected with the first transistor;

the second transistor, disposed on and in the first semiconductor layer, wherein the second transistor comprises a second gate dielectric layer having a thickness less than a thickness of the first gate dielectric layer;

a second insulating layer disposed on the second transistor;

second interconnect structures disposed in the second insulating layer, wherein at least one of the second interconnect structures is electrically connected with the second transistor, wherein at least one of the second interconnect structures is connected with at least one of the first interconnect structures by extending through the isolation structure; and

a second semiconductor structure disposed on the first semiconductor structure, wherein the second semiconductor structure comprises memory cells coupled to the first transistor and the second transistor.

2 . The memory device of claim 1 , wherein the first transistor is configured to operate with a first voltage and the second transistor is configured to operate with a second voltage, wherein the second voltage is lower than the first voltage.

3 . The memory device of claim 1 , the first transistor comprises a first threshold voltage and the second transistor comprises a second threshold voltage with a magnitude lower than a magnitude of the first threshold voltage.

4 . The memory device of claim 1 , wherein the first semiconductor layer comprises a thickness less than 100 nm.

5 . The memory device of claim 1 , wherein the second transistor is a fully-depleted transistor having at least a portion of an active device region fully depleted during operation.

6 . The memory device of claim 5 , wherein the second transistor comprises a source/drain region vertically extending through the first semiconductor layer.

7 . The memory device of claim 1 , wherein the second semiconductor structure further comprises:

a film stack of alternating conductive and dielectric layers; and

memory strings vertically penetrating through the film stack.

8 . The memory device of claim 7 , wherein the second semiconductor structure further comprises:

a third insulating layer covering the film stack; and

third interconnect structures in the third insulating layer, wherein the third interconnect structures are electrically connected with a word line, a bit line or at least one of the second interconnect structures.

9 . The memory device of claim 8 , further comprising:

a second semiconductor layer;

a through-substrate-interconnect penetrating through the second semiconductor layer; and

a contact pad electrically connected with the through-substrate-interconnect, wherein the contact pad and the film stack are on opposite sides of the second semiconductor layer.

10 . The memory device of claim 9 , further comprising:

a contact vertical-interconnect-access (VIA) penetrating through the third insulating layer, wherein the contact VIA is connected with the through-substrate-interconnect and at least one of the second interconnect structures.

11 . A memory system, comprising:

a memory device, comprising:

a first semiconductor structure, comprising:

a first transistor comprising a first gate dielectric layer;

a first semiconductor layer disposed on the first transistor;

an isolation structure vertically penetrating through the first semiconductor layer to electrically isolate a second transistor;

a first insulating layer disposed on the first transistor;

first interconnect structures disposed in the first insulating layer, wherein at least one of the first interconnect structures is electrically connected with the first transistor;

the second transistor, disposed on and in the first semiconductor layer, wherein the second transistor comprises a second gate dielectric layer having a thickness less than a thickness of the first gate dielectric layer;

a second insulating layer disposed on the second transistor;

second interconnect structures disposed in the second insulating layer, wherein at least one of the second interconnect structures is electrically connected with the second transistor, wherein at least one of the second interconnect structures is connected with at least one of the first interconnect structures by extending through the isolation structure; and

a second semiconductor structure disposed on the first semiconductor structure, wherein the second semiconductor structure comprises memory cells coupled to the first transistor and the second transistor; and

a memory controller configured to send commands to the memory device for programming the memory device.

12 . The memory system of claim 11 , wherein the first transistor is configured to operate with a first voltage and the second transistor is configured to operate with a second voltage, wherein the second voltage is lower than the first voltage.

13 . The memory system of claim 11 , the first transistor comprises a first threshold voltage and the second transistor comprises a second threshold voltage with a magnitude lower than a magnitude of the first threshold voltage.

14 . The memory system of claim 11 , wherein the first semiconductor layer comprises a thickness less than 100 nm.

15 . The memory system of claim 11 , wherein the second transistor is a fully-depleted transistor having at least a portion of an active device region fully depleted during operation.

16 . The memory system of claim 15 , wherein the second transistor comprises a source/drain region vertically extending through the first semiconductor layer.

17 . The memory system of claim 11 , wherein the second semiconductor structure further comprises:

a film stack of alternating conductive and dielectric layers; and

memory strings vertically penetrating through the film stack.

18 . The memory system of claim 17 , wherein the second semiconductor structure further comprises:

a third insulating layer covering the film stack; and

third interconnect structures in the third insulating layer, wherein the third interconnect structures are electrically connected with a word line, a bit line or at least one of the second interconnect structures.

19 . The memory system of claim 18 , further comprising:

a second semiconductor layer;

a through-substrate-interconnect penetrating through the second semiconductor layer; and

a contact pad electrically connected with the through-substrate-interconnect, wherein the contact pad and the film stack are on opposite sides of the second semiconductor layer.

20 . The memory system of claim 19 , further comprising:

a contact vertical-interconnect-access (VIA) penetrating through the third insulating layer, wherein the contact VIA is connected with the through-substrate-interconnect and at least one of the second interconnect structures.