Nonvolatile memory device with reduced lateral charge

1 . A nonvolatile memory device comprising:

a channel layer extending in a first direction;

a plurality of gate electrodes and a plurality of insulating layers that are spaced apart from the channel layer and being alternately arranged in the first direction;

a charge trap layer between the channel layer and the plurality of gate electrodes; and

a charge tunneling layer between the channel layer and the charge trap layer,

wherein the charge trap layer comprises a two-dimensional material, and the two-dimensional material comprises a crystalline structure having atoms arranged in an x-y plane that is inclined with respect to a surface of the channel layer.

2 . The nonvolatile memory device of claim 1 , wherein the two-dimensional material comprises a chalcogenide compound.

3 . The nonvolatile memory device of claim 2 , wherein a chemical formular of the chalcogenide compound is M 1 N x , the M is one of Ti, Hf, Zr, V, Nb, Ta, Mo, W, Tc, Re, Pd, Pt, Bi, Sb, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu, the N is one of S, Se, and Te, and the x is greater than or equal to 1 and less than or equal to 3.

4 . The nonvolatile memory device of claim 1 , wherein the two-dimensional material comprises a metal oxide.

5 . The nonvolatile memory device of claim 4 , wherein the metal oxide comprises at least one selected from the group including TiO x (1≤x≤2), MnO 2 , TiNbO 5 , Ti 2 NbO 7 , TiTaO 5 , Nb 3 O 8 , Nb 6 O 17 , TaO 3 , LaNb 2 O 7 , La 0.90 Eu 0.05 Nb 2 O 7 , Eu 0.56 Ta 2 O 7 , SrTa 2 O 7 , Bi 2 SrTa 2 O 9 , Ca 2 Nb 3 O 10 , Sr 2 Nb 3 O 10 , NaCaTa 3 O 10 , CaLaNb 2 TiO 10 , La 2 Ti 2 NbO 10 , Ba 5 Ta 4 O 15 , W 2 O 7 , RuO 2 , and Cs 4 W 11 O 36 .

6 . The nonvolatile memory device of claim 1 , wherein the two-dimensional material comprises graphene.

7 . The nonvolatile memory device of claim 1 , wherein the two-dimensional material comprises boron nitride.

8 . The nonvolatile memory device of claim 1 , wherein the two-dimensional material comprises at least one metal cation and at least one anion, and a ratio of a number of metal cations with respect to a number of anions at an interface of the charge trap layer is greater than a ratio of the number of the metal cations with respect to the number of anions in all of the charge trap layer.

9 . The nonvolatile memory device of claim 1 , wherein the charge trap layer defines a void region.

10 . The nonvolatile memory device of claim 1 , wherein the charge trap layer comprises silicon (Si).

11 . The nonvolatile memory device of claim 1 , wherein

the crystalline structure of the two-dimensional material comprises a plurality of atomic layers, and

a distance between adjacent atomic layers of the crystalline structure of the plurality of atomic layers is greater than or equal to 0.1 nm and less than or equal to 5 nm.

12 . The nonvolatile memory device of claim 1 , wherein the two-dimensional material comprises at least one metal atom, and the at least one metal atom is in contact with the charge tunneling layer.

13 . A nonvolatile memory device comprising:

a channel layer extending in a first direction;

a plurality of gate electrodes and a plurality of insulating lavers that are spaced apart from the channel layer and being alternately arranged in the first direction;

a charge trap layer between the channel layer and the plurality of gate electrodes; and

a charge tunneling layer between the channel layer and the charge trap layer,

wherein the charge trap layer comprises a two-dimensional material, and the two-dimensional material comprises a crystalline structure that is inclined with respect to the channel layer,

wherein the charge trap layer comprises a region having the crystalline structure in which an angle formed between an x-y plane of the two-dimensional material and the channel layer is greater than or equal to 45 degrees and less than or equal to 90 degrees.

14 . The nonvolatile memory device of claim 13 , wherein the two-dimensional material comprises a chalcogenide compound.

15 . The nonvolatile memory device of claim 14 , wherein a chemical formular of the chalcogenide compound is M 1 N x , the M is one of Ti, Hf, Zr, V, Nb, Ta, Mo, W, Tc, Re, Pd, Pt, Bi, Sb, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu, the N is one of S, Se, and Te, and the x is greater than or equal to 1 and less than or equal to 3.

16 . The nonvolatile memory device of claim 13 , wherein the two-dimensional material comprises a metal oxide.

17 . The nonvolatile memory device of claim 13 , wherein the two-dimensional material comprises Mxene.

18 . The nonvolatile memory device of claim 13 , wherein the two-dimensional material comprises at least one metal atom, and the at least one metal atom is in contact with the charge tunneling layer.

19 . A nonvolatile memory device comprising:

a channel layer extending in a first direction;

a plurality of gate electrodes and a plurality of insulating lavers that are spaced apart from the channel layer and being alternately arranged in the first direction;

a charge trap layer between the channel layer and the plurality of gate electrodes; and

a charge tunneling layer between the channel layer and the charge trap laver,

wherein the charge trap layer comprises a two-dimensional material, and the two-dimensional material comprises a crystalline structure that is inclined with respect to the channel layer, wherein

the two-dimensional material comprises Mxene.

20 . The nonvolatile memory device of claim 19 , wherein the Mxene comprises at least one selected from the group including Ti 2 C, V 2 C, Nb 2 C, Mo 2 C, Ti 3 C 2 , Zr 3 C 2 , Nb 4 C 3 , Ta 4 C 3 , Ti 4 N 3 , TiNbC, (Ti 0.5 Nb 0.5 ) 2 C, (V 0.5 Cr 0.5 ) 3 C 2 , Ti 3 CN, Mo 2 TiC 2 , Mo 2 ScC 2 , Cr 2 TiC 2 , Mo 2 Ti 2 C 3 , (Nb 0.8 Ti 0.2 ) 4 C 3 , and (Nb 0.8 Zr 0.2 ) 4 C 3 .