Semiconductor memory device for performing blind program operation and method of operating the same

1 . A method of operating a semiconductor memory device, comprising:

performing at least one normal program loop on a first memory cell, among a plurality of memory cells included in a page selected as a program target, having an N-th program state, among a plurality of program states, as a target program state; and

performing at least one blind program loop on the first memory cell,

wherein, while the at least one blind program loop is being performed, a target data pattern that is stored in a data latch of a first page buffer coupled to the first memory cell and that corresponds to the N-th program state is changed to a first data pattern corresponding to a first program state that is lower than the N-th program state, among the plurality of program states, and

wherein N is a natural number equal to or greater than 2.

2 . The method according to claim 1 ,

wherein, while the at least one normal program loop is being performed, the data latch of the first page buffer stores the target data pattern corresponding to the N-th program state.

3 . The method according to claim 1 ,

wherein a verify operation on the first memory cell is performed in the normal program loop and is not performed in the blind program loop.

4 . The method according to claim 1 , wherein performing the at least one blind program loop comprises:

changing the target data pattern stored in the data latch of the first page buffer to the first data pattern;

increasing a threshold voltage of the first memory cell by applying a program voltage to a word line coupled to the first memory cell; and

updating a value stored in the first page buffer.

5 . The method according to claim 4 , wherein updating the value stored in the first page buffer comprises:

changing the first data pattern stored in the data latch of the first page buffer to a second data pattern corresponding to a second program state, among the plurality of program states.

6 . The method according to claim 5 , further comprising:

determining whether the value stored in the data latch has reached a preset value.

7 . The method according to claim 6 , further comprising:

terminating a program operation on the first memory cell in response to a determination that the value stored in the data latch has reached the preset value.

8 . The method according to claim 6 , further comprising:

re-increasing the threshold voltage of the first memory cell by re-applying a program voltage to the word line coupled to the first memory cell in response to a determination that the value stored in the data latch has not reached the preset value; and

re-updating the value stored in the first page buffer,

wherein N is a natural number equal to or greater than 3.

9 . The method according to claim 8 , wherein re-updating the value stored in the first page buffer comprises:

changing the first data pattern stored in the data latch of the first page buffer to the second data pattern corresponding to the second program state, among the plurality of program states.

10 . The method according to claim 1 , further comprising:

after the at least one normal program loop is performed, determining whether the threshold voltage of the first memory cell is higher than a reference voltage,

wherein the at least one blind program loop begins in response to a determination that the threshold voltage of the first memory cell is higher than the reference voltage.

11 . A semiconductor memory device, comprising:

a plurality of memory cells, each storing M bits;

a plurality of page buffers coupled to the plurality of memory cells through bit lines, respectively, and configured to perform a program operation such that a threshold voltage of each of selected memory cells, among the plurality of memory cells, is included in a corresponding program state, among an erase state and first to (2 M −1)-th program states; and

a control logic configured to control a first page buffer, among the plurality of page buffers, coupled to a first memory cell corresponding to the (2 M −1)-th program state such that, while the program operation is being performed by the plurality of page buffers, a normal program loop is performed on the first memory cell and such that, after the normal program loop is performed, a blind program loop is performed on the first memory cell,

wherein M is a natural number equal to or greater than 2,

wherein while the normal program loop is being performed, a data latch of the first page buffer stores a target data pattern corresponding to the (2 M −1)-th program state, and

wherein while the blind program loop is being performed, the first page buffer changes the target data pattern stored in the data latch to a first data pattern corresponding to the first program state.

12 . The semiconductor memory device according to claim 11 ,

wherein a verify operation on the first memory cell is performed in the normal program loop and is not performed in the blind program loop.

13 . The semiconductor memory device according to claim 12 ,

wherein, after a first blind program loop is performed on the first memory cell, the first page buffer changes the first data pattern stored in the data latch to a second data pattern.

14 . The semiconductor memory device according to claim 13 ,

wherein the second data pattern is a data pattern corresponding to the erase state, and

wherein the control logic controls the first page buffer such that, after the first blind program loop is performed, a program operation on the first memory cell is terminated.

15 . The semiconductor memory device according to claim 13 ,

wherein the second data pattern is a data pattern corresponding to a second program state, among the first to (2 M −1)-th program states.

16 . The semiconductor memory device according to claim 15 ,

wherein, after a second blind program loop is performed on the first memory cell, the first page buffer changes the second data pattern stored in the data latch to a third data pattern.

17 . The semiconductor memory device according to claim 16 ,

wherein the third data pattern is a data pattern corresponding to the erase state, and

wherein the control logic controls the first page buffer such that, after the second blind program loop is performed, the program operation on the first memory cell is terminated.

18 . The semiconductor memory device according to claim 16 ,

wherein the third data pattern is a data pattern corresponding to a third program state, among the first to (2 M −1)-th program states.

19 . The semiconductor memory device according to claim 11 ,

wherein the control logic controls the first page buffer such that, when a threshold voltage of the first memory cell is lower than a reference voltage, a normal program loop is performed on the first memory cell, and when the threshold voltage of the first memory cell is higher than the reference voltage, a blind program loop is performed on the first memory cell.

20 . The semiconductor memory device according to claim 19 ,

wherein the reference voltage is a verify voltage for verifying a (2 M −2)-th program state, among the first to (2 M −1)-th program states.