State dependent suspend-resume-go for performance improvement in a memory device

1 . A method of performing a programming operation in a memory device, comprising steps of:

preparing a memory block that includes an array of memory cells that are arranged in a plurality of word lines;

in a program loop, applying a programming pulse at a programming voltage VPGM to a selected word line of the plurality of word lines to program a plurality of the memory cells of the selected word line to a target data state of a plurality of data states and wherein each data state of the plurality of data states is associated with a unique threshold;

suspending the programming operation for a suspension duration and then resuming the programming operation;

before a next program loop, comparing the suspend duration to the threshold that is unique to the target data state;

in response to the suspension duration being less than or equal to the threshold that is unique to the target data state, incrementally increasing the programming voltage VPGM by a baseline step size dVPGM; and

in response to the suspension duration being greater than the threshold that is unique to the target data state, incrementally increasing the programming voltage VPGM by a reduced step size dVPGM_SRG that is less than the baseline step size dVPGM.

2 . The method as set forth in claim 1 , wherein the threshold duration of at least one of the plurality of data states, which is at a higher voltage range, is less than the threshold duration of at least one of the plurality of data states, is at a lower voltage range.

3 . The method as set forth in claim 1 , further including a step of determining a delay time that is from a start of the programming operation to a beginning of the step of suspending the programming operation, and wherein the target data state is determined based on the delay time.

4 . The method as set forth in claim 1 , wherein in response to the target data state being a first programmed data states of the plurality of data states, then the step size is a baseline step size dVPGM.

5 . The method as set forth in claim 1 , wherein in response to the target data state being a last programmed data state of the plurality of data states, then the step size is a baseline step size dVPGM.

6 . The method as set forth in claim 1 , wherein the program loop further includes a verify operation that includes at least a first verify pulse at a verify low voltage and a second verify pulse at a verify high voltage, and further including the step of:

applying a quick pass write (QPW) biasing voltage to a bit line coupled to a selected memory cell of the selected word line in response to the selected memory cells being detected in the verify operation as having a threshold voltage that is between the verify low voltage and the verify high voltage.

7 . A memory device, comprising:

a memory block that includes an array of memory cells that are arranged in a plurality of word lines;

circuitry that is configured to program the memory cells of a selected word line of the plurality of word lines, during programming, the circuitry being configured to;

in a program loop, apply a programming pulse at a programming voltage VPGM to a selected word line of the plurality of word lines to program a plurality of the memory cells of the selected word line to a target data state of a plurality of data states, each data state of the plurality of data states being associated with a unique threshold;

suspend the programming operation for a suspension duration and then resume the programming operation;

before a next program loop, compare the suspend duration to the threshold that is unique to the target data state;

in response to the suspension duration being less than or equal to the threshold that is unique to the target data state, incrementally increase the programming voltage VPGM by a baseline step size dVPGM; and

in response to the suspension duration being greater than the threshold that is unique to the target data state, incrementally increase the programming voltage VMPGM by a reduced step size dVPGM_SRG that is less than the baseline step size dVPGM.

8 . The memory device as set forth in claim 7 , wherein the threshold duration of at least one of the plurality of data states, which is at a higher voltage range, is less than the threshold duration of at least one of the plurality of data states, is at a lower voltage range.

9 . The memory device as set forth in claim 7 , wherein the circuitry is further configured to determine a delay time that is from a start of the programming operation to a beginning of the step of suspending the programming operation and to determine the target data state based on the delay time.

10 . The memory device as set forth in claim 7 , wherein in response to the target data state being a first programmed data states of the plurality of data states, then the step size is a baseline step size dVPGM.

11 . The memory device as set forth in claim 7 , wherein in response to the target data state being a last programmed data state of the plurality of data states, then the step size is a baseline step size dVPGM.

12 . The memory device as set forth in claim 7 , wherein the program loop further includes the circuitry performing a verify operation that includes at least a first verify pulse at a verify low voltage and a second verify pulse at a verify high voltage, and the circuitry is further configured to:

apply a quick pass write (QPW) biasing voltage to a bit line coupled to a selected memory cell of the selected word line in response to the selected memory cells being detected in the verify operation as having a threshold voltage that is between the verify low voltage and the verify high voltage.

13 . An apparatus, comprising:

a memory block that includes an array of memory cells that are arranged in a plurality of word lines;

a programming means for programming the memory cells of a selected word line of the plurality of word lines, during programming, the programming means being configured to;

in a program loop, apply a programming pulse at a programming voltage VPGM to a selected word line of the plurality of word lines to program a plurality of the memory cells of the selected word line to a target data state of a plurality of data states, wherein each data state of the plurality of data states is associated with a unique threshold;

suspend the programming operation for a suspension duration and then resuming the programming operation;

before a next program loop, compare the suspend duration to the threshold that is unique to the target data state,

in response to the suspension duration being less than or equal to the threshold that is unique to the target data state, incrementally increase the programming voltage VPGM by a baseline step size dVPGM; and

in response to the suspension duration being greater than the threshold that is unique to the target data state, incrementally increase the programming voltage VMPGM by a reduced step size dVPGM_SRG that is less than the baseline step size dVPGM.

14 . The apparatus as set forth in claim 13 , wherein the threshold duration of at least one of the plurality of data states, which is at a higher voltage range, is less than the threshold duration of at least one of the plurality of data states, is at a lower voltage range.