Calculation unit splitting for NAND in-memory compute

1 . An apparatus comprising:

one or more control circuits configured to connect to a three-dimensional (3D) NAND memory structure, the 3D NAND memory structure having a plurality of bit lines and NAND strings associated with the plurality of bit lines, the one or more control circuits configured to:

organize a plurality of calculation units based on a characteristic of individual NAND memory cell transistors on the NAND strings in the 3D memory structure, each calculation unit of the plurality of calculation units comprising a plurality of the individual NAND memory cell transistors, wherein at least one of the individual NAND memory cell transistors of a first calculation unit of the plurality of calculation units separates two of the plurality of NAND memory cell transistors of a second calculation unit of the plurlity of calcultion units;

program threshold voltages of the plurality of the individual NAND memory cell transistors of the plurality of calculation units to represent a first vector, the plurality of the programmed NAND memory cell transistors residing on at least one NAND string in the 3D memory structure, each NAND string of the at least one NAND string connected to a corresponding bit line in the 3D memory structure;

apply voltages to gates of the plurality of the programmed NAND memory cell transistors of the plurality of calculation units to represent a second vector;

sense a current of the corresponding bit line connected to each NAND string of the at least one NAND string that results from applying the voltages to the gates of the plurality of the programmed NAND memory cell transistors of the plurality of calculation units; and

determine a result of multiplying the first vector by the second vector based on the current of the corresponding bit line connected to each NAND string of the at least one NAND string

vector by the second vector based on the current of each of the at least one bit lines.

2 . The apparatus of claim 1 , wherein the one or more control circuits are further configured to:

measure the characteristic of the individual NAND memory cell transistors, the characteristic being an operational characteristic; and

form each calculation unit of the plurality of calculation units from the individual NAND memory cell transistors that are within a tolerance of each other in the operational characteristic.

3 . The apparatus of claim 1 , wherein:

the characteristic of the individual NAND memory cell transistors comprises a drain to source current for a set of in-memory compute operating conditions.

4 . The apparatus of claim 3 , wherein the one or more control circuits are configured to:

measure the drain to source current for the set of in-memory compute operating conditions for the individual NAND memory cell transistors; and

form each calculation unit of the plurality of calculation units from the individual NAND memory cell transistors that are within a tolerance of each other in the drain to source current for the set of in-memory compute operating conditions.

5 . The apparatus of claim 1 , wherein:

the characteristic of the individual NAND memory cell transistors comprises a drain to source current for a target threshold voltage of the individual NAND memory cell transistors and a gate to source voltage of the individual NAND memory cell transistors.

6 . The apparatus of claim 1 , wherein:

the characteristic of the individual NAND memory cell transistors comprises a physical characteristic upon which a drain-to-source current of the individual NAND memory cell transistors depend; and

the one or more control circuits are further configured to form each calculation unit of the plurality of calculation units from the individual NAND memory cell transistors that are within a tolerance of each other in the physical characteristic.

7 . The apparatus of claim 6 , wherein the physical characteristic of the individual NAND memory cell transistors comprises a tunnel oxide thickness of the individual NAND memory cell transistors, the one or more control circuits are further configured to form each calculation unit from NAND memory cell transistors that are within a tolerance of each other in the tunnel oxide thickness.

8 . The apparatus of claim 6 , wherein the physical characteristic of the individual NAND memory cell transistors comprises a tunnel oxide capacitance of the individual NAND memory cell transistors, the one or more control circuits are further configured to form each calculation unit of the plurality of calculation units from the individual NAND memory cell transistors that are within a tolerance of each other in the tunnel oxide capacitance.

9 . The apparatus of claim 6 , wherein the physical characteristic of the of the individual NAND memory cell transistors comprises a length of the individual NAND memory cell transistors, the one or more control circuits are further configured to form each calculation unit of the plurality of calculation units from the individual NAND memory cell transistors that are within a tolerance of each other in transistor length.

10 . The apparatus of claim 6 , wherein the physical characteristic of the individual NAND memory cell transistors comprises a width of the individual NAND memory cell transistors, the one or more control circuits are further configured to form each calculation unit of the plurality of calculation units from the individual NAND memory cell transistors that are within a tolerance of each other in transistor width.

11 . The apparatus of claim 1 , wherein each calculation unit of the plurality of calculation units comprises two NAND memory cell transistors on the same NAND string, wherein the at least one individual NAND memory cell transistor of the first calculation unit separates the two NAND memory cell transistors of the second calculation unit on the same NAND string.

12 . The apparatus of claim 11 , wherein a first individual NAND memory cell transistor of the plurality of the individual NAND memory cell transistors of the second calculation unit resides on a first NAND string and a second individual NAND memory cell transistor of the plurality of the individual NAND memory cell transistors of the second calculation unit resides on a second NAND string, the first individual NAND memory cell transistor and the second individual NAND memory cell transistor each connected to a first word line in the 3D NAND memory structure, wherein a third individual NAND memory cell transistor of the plurality of NAND memory cell transistors of the first calculation unit resides on a third NAND string connected to the first word line, the third NAND string is between the first NAND string and the second NAND string.

13 . A method for performing in-memory computations, the method comprising:

measuring a characteristic of individual NAND memory cell transistors in a three-dimensional (3D) NAND memory structure;

forming a plurality of calculation units based on the characteristic of the individual NAND memory cell transistors, each calculation unit of the plurality of calculation units comprising a plurality of the individual NAND memory cell transistors, wherein at least one of the individual NAND memory cell transistors of a first calculation unit of the plurality of calculation units separates two of the plurality of the individual NAND memory cell transistors of a second calculation unit of the plurality of calculation unit;

programming threshold voltages of the plurality of the individual NAND memory cell transistors of the plurality of calculation units to represent a first vector, the plurality of the programmed NAND memory cell transistors residing on at least one NAND string in the three-dimensional NAND memory structure, each NAND string of the at least one NAND string connected to a corresponding bit line in the 3D memory structure;

applying voltages to gates of the plurality of the programmed NAND memory cell transistors of the plurality of calculation units to represent a second vector;

sensing a current of the corresponding bit line connected to each NAND string of the at least one NAND string that results from applying the voltages to the gates of the plurality of the programmed NAND memory cell transistors of the plurality of calculation units; and

determining a dot product of the first vector times the second vector based on the current of the corresponding bit line connected to each NAND string of the at least one NAND string.

14 . The method of claim 13 , wherein:

measuring the characteristic of the individual NAND memory cell transistors in the three-dimensional NAND memory structure comprises measuring an operational characteristic of the individual NAND memory cell transistors; and

forming the plurality of calculation units based on the characteristic of the individual NAND memory cell transistors comprises forming each calculation unit from the individual NAND memory cell transistors that are within a tolerance of each other in the operational characteristic.

15 . The method of claim 14 , wherein:

measuring the operational characteristic of the individual NAND memory cell transistors comprises measuring a drain to source current for typical in-memory compute conditions; and

forming each calculation unit of the plurality of calculation units from the individual NAND memory cell transistors that are within a tolerance of each other in the operational characteristic comprises forming each calculation unit of the plurality of calculation units from the individual NAND memory cell transistors that are within a tolerance of each other in the drain to source current.

16 . A NAND memory system comprising:

a three-dimensional NAND memory structure having bit lines and NAND strings associated with the bit lines, each NAND string having individual NAND memory cell transistors; and

one or more control circuits in communication with the three-dimensional NAND memory structure, the one or more control circuits configured to:

form a plurality of calculation units based on a drain-to-source current of the individual NAND memory cell transistors for equivalent operating parameters during an in-memory computation, each calculation unit of the plurality of calculation units having a plurality of the individual NAND memory cell transistors on a NAND string in the three-dimensional NAND memory structure; and

perform the in-memory computation using the plurality of calculation units.

17 . The NAND memory system of claim 16 , wherein the one or more control circuits are configured to:

form each calculation unit of the plurality of calculation units to include the individual NAND memory cell transistors having a drain-to-source current for the equivalent operating parameters that is within a tolerance of each other.

18 . The NAND memory system of claim 16 , wherein the equivalent operating parameters comprises the same Vt and the same gate-to-source voltage.

19 . The NAND memory system of claim 16 , wherein the one or more control circuits are configured to:

program threshold voltages of the plurality of the individual NAND memory cell transistors of the plurality of the calculation units to represent a first vector, the plurality of the programmed NAND memory cell transistors of the plurality of the calculation units residing on one or more selected NAND strings connected to a corresponding one or more bit lines;

apply voltages to gates of the plurality of the programmed NAND memory cell transistors of the plurality of the calculation units to represent a second vector;

sense a current for each bit line of the one or more bit lines that results from applying the voltages to the gates of plurality of the programmed NAND memory cell transistors of the plurality of the calculation units; and

determine a dot product of the first vector times the second vector based on the current for each bit line of the one or more bit lines.