Suspend-resume-go techniques for memory devices

1 . A method of performing an erase operation in a memory device having a memory block that includes an array of memory cells that are arranged in a plurality of word lines, the method comprising the steps of:

initiating an erase operation of the memory block;

during the erase operation, applying at least one erase pulse to the memory block to erase memory cells of a plurality of selected word lines of the plurality of word lines, the plurality of selected word lines including a plurality of selected memory cells;

responsive to a suspension event prior to completion of the erase operation, suspending the erase operation by suspending the at least one erase pulse for a suspend duration;

after the suspend duration and before applying a next erase pulse to the memory block, performing an erase-verify operation on only a first portion of the selected memory cells of the memory block;

in response to a determination that the first portion of the selected memory cells did not pass the erase-verify operation, resuming the erase operation by applying the next erase pulse to the memory block and then performing the erase-verify operation on a remaining portion of the selected memory cells of the memory block; and

in response to a determination that the first portion of the selected memory cells passed the erase-verify operation, completing the erase operation without applying the next erase pulse to the memory block.

2 . The method as set forth in claim 1 , further including the steps of:

during the step of performing the erase-verify operation on only the first portion of the selected memory cells, counting a number of memory cells that fail the erase-verify operation to establish a count; and

determining an erase pulse duration for the next erase pulse as a function of the count.

3 . The method as set forth in claim 2 , wherein the step of determining the erase pulse duration for the next erase pulse as a function of the count includes the steps of:

comparing the count to a predetermined threshold,

setting the erase pulse duration at a first timeframe in response to the count being above the predetermined threshold, and

setting the erase pulse duration at a second timeframe in response to the count being below the predetermined threshold, and wherein the second timeframe is less than the first timeframe.

4 . The method as set forth in claim 3 , wherein the first portion of the selected memory cells includes the memory cells of a single string of a plurality of strings in the memory block, and the remaining portion of the selected memory cells includes remaining strings of the memory block.

5 . The method as set forth in claim 4 , wherein in response to any of the remaining strings of the memory block failing the erase-verify operation, then the method further includes the step of setting the erase pulse duration at a third timeframe that is less than the second timeframe.

6 . The method as set forth in claim 1 , wherein the first portion of selected memory cells includes the memory cells of a single string of a plurality of strings in the memory block.

7 . The method as set forth in claim 1 , wherein the plurality of selected word lines include all data word lines in the memory block.

8 . A memory device comprising:

a memory block with an array of memory cells that are arranged in a plurality of word lines, the plurality of word lines including a plurality of selected word lines containing selected memory cells to be erased;

circuitry for erasing the selected memory cells in an erase operation, wherein, during the erase operation, the circuitry is configured to;

apply at least one erase pulse to the memory block to erase the selected memory cells;

responsive to a suspension event prior to completion of the erase operation, suspend the erase operation by suspending the at least one erase pulse for a suspend duration;

after the suspend duration and before applying a next erase pulse to the memory block, perform an erase-verify operation on only a first portion of the selected memory cells of the memory block;

in response to a determination that the first portion of the selected memory cells did not pass the erase-verify operation, resume the erase operation by applying the next erase pulse to the memory block and then performing the erase-verify operation on a remaining portion of the selected memory cells of the memory block; and

in response to a determination that the first portion of the selected memory cells passed the erase-verify operation, complete the erase operation without applying the next erase pulse to the memory block.

9 . The memory device as set forth in claim 8 , wherein:

during the step of performing the erase-verify operation on only the first portion of the selected memory cells, the circuitry counts a number of memory cells that fail the erase-verify operation to establish a count and determines an erase pulse duration for the next erase pulse as a function of the count.

10 . The memory device as set forth in claim 9 , wherein while determining the erase pulse duration for the next erase pulse as a function of the count, the circuitry:

compares the count to a predetermined threshold, and

sets the erase pulse duration at a first timeframe in response to the count being above the predetermined threshold, and

sets the erase pulse duration at a second timeframe in response to the count being below the predetermined threshold, and wherein the second timeframe is less than the first timeframe.

11 . The memory device as set forth in claim 10 , wherein the first portion of the selected memory cells includes the memory cells of a single string of a plurality of strings in the memory block, and the remaining portion of the selected memory cells includes remaining strings of the memory block.

12 . The memory device as set forth in claim 11 , wherein in response to any of the remaining strings of the memory block failing the erase-verify operation, then the circuitry sets the erase pulse duration at a third timeframe that is less than the second timeframe.

13 . The memory device as set forth in claim 8 , wherein the first portion of selected memory cells includes the memory cells of a single string of a plurality of strings in the memory block.

14 . The memory device as set forth in claim 8 , wherein the plurality of selected word lines include all data word lines in the memory block.

15 . An apparatus, comprising:

a memory block with an array of memory cells that are arranged in a plurality of word lines, the plurality of word lines including a plurality of selected word lines containing selected memory cells to be erased;

erasing means for erasing the selected memory cells in an erase operation, during the erase operation, the erasing means being configured to;

apply at least one erase pulse to the memory block to erase the selected memory cells;

responsive to a suspension event prior to completion of the erase operation, suspend the erase operation by suspending the at least one erase pulse for a suspend duration;

after the suspend duration and before applying a next erase pulse to the memory block, perform an erase-verify operation on only a first portion of the selected memory cells of the memory block;

in response to a determination that the first portion of the selected memory cells did not pass the erase-verify operation, resume the erase operation by applying the next erase pulse to the memory block and then performing the erase-verify operation on a remaining portion of the selected memory cells of the memory block; and

in response to a determination that the first portion of the selected memory cells passed the erase-verify operation, complete the erase operation without applying the next erase pulse to the memory block.

16 . The apparatus as set forth in claim 15 , wherein:

while performing the erase-verify operation on only the first portion of the selected memory cells, the erasing means counts a number of memory cells that fail the erase-verify operation to establish a count and determines an erase pulse duration for the next erase pulse as a function of the count.

17 . The apparatus as set forth in claim 16 , wherein while determining the erase pulse duration for the next erase pulse as a function of the count, the erasing means:

compares the count to a predetermined threshold, and

sets the erase pulse duration at a first timeframe in response to the count being above the predetermined threshold, and

sets the erase pulse duration at a second timeframe in response to the count being below the predetermined threshold, and wherein the second timeframe is less than the first timeframe.

18 . The apparatus as set forth in claim 17 , wherein the first portion of the selected memory cells includes the memory cells of a single string of a plurality of strings in the memory block, and the remaining portion of the selected memory cells includes remaining strings of the memory block.

19 . The apparatus as set forth in claim 18 , wherein in response to any of the remaining strings of the memory block failing the erase-verify operation, then the erasing means sets the erase pulse duration at a third timeframe that is less than the second timeframe.

20 . The apparatus as set forth in claim 17 , wherein the first portion of selected memory cells includes the memory cells of a single string of a plurality of strings in the memory block.