Staggered triggering controller
A non-volatile memory device comprises an array of non-volatile memory cells, a controller in communication with the non-volatile memory cell, a row driver including a plurality of high-voltage switches for applying high-voltages to non-volatile memory cells, a column driver including a plurality of sensing circuits for monitoring the data of the non-volatile memory cells; and, a plurality of time delay circuits, wherein the time delay circuit is configured to reduce peak current caused by simultaneous application of high voltages to the non-volatile memory cells or simultaneous detection of current flowing across bit lines of the non-volatile memory cells.
1 . A non-volatile memory device
comprising: an array of non-volatile memory cells;
a controller in communication with the non-volatile memory cell,
a row driver including a plurality of high-voltage switches for applying high-voltages to non-volatile memory cells;
a column driver including a plurality of sensing circuits for monitoring the data of the non-volatile memory cells; and,
a plurality of time delay circuits, wherein the time delay circuit is configured to reduce peak current caused by simultaneous application of high voltages to the non-volatile memory cells or simultaneous detection of current flowing across bit lines of the non-volatile memory cells,
wherein the sensing circuit comprises a pair of cross connected CMOS inverters in that an output node of a first CMOS inverter is coupled to an input node of a second CMOS inverter,
wherein a PMOS circuit within the first CMOS inverter is connected to a first enable PMOS circuit in parallel and a PMOS circuit within the second CMOS inverter is connected to a second enable PMOS circuit in parallel;
wherein (1) a NMOS circuit within the first CMOS inverter is connected to a first input NMOS circuit in series, a gate terminal of the first input NMOS circuit is connected to bit line and (2) a NMOS circuit within the second CMOS inverter is connected to a second input NMOS circuit in series, a gate terminal of the second input NMOS circuit is connected to a voltage reference line; and
wherein the first and second input NMOS circuits are connected to a third NMOS circuit and a drain terminal of the third NMOS circuit is shared by the first and second input NMOS circuits.
2 . The non-volatile memory device of claim 1 , wherein the non-volatile memory device further includes a charge pump circuit for pumping up a plurality of voltages from a predefined reference voltage, said charge pump circuit connected to the plurality of high voltage switches and the controller.
3 . The non-volatile memory device of claim 2 , wherein the high voltage switch transmits an input signal to the non-volatile memory cell when activated by the controller, wherein said input signal can vary from the predefined reference voltage, two times the reference voltage, three times the reference voltage, and four times the reference voltage to the non-volatile memory cell.
4 . The non-volatile memory device of claim 1 , wherein an enable line connecting the controller and the sensing circuit is configured to connect gate terminals of the first and second enable PMOS circuits and a gate terminal of the third NMOS circuit.
5 . The non-volatile memory device of claim 1 , wherein the row driver includes the time delay circuits connected in series, each time delay circuit arranged between all or some of the pairs of high-voltage (HV) switches.
6 . The non-volatile memory device of claim 1 , wherein the row driver includes the time delay circuits connected in series, each said time delay circuits arranged between all or some of groups including a plurality of the HV switches.
7 . The non-volatile memory device of claim 1 , wherein the controller includes:
a plurality of enable lines coupling the controller to each group with a plurality of the HV switches within the row driver, and
a plurality of time delay circuits connected in series with an identical delay value arranged between each of the enable lines such that a plurality of enable signals are sequentially sent to the groups of HV switches coupled through the enable lines, respectively.
8 . The non-volatile memory device of claim 1 , wherein the column driver includes the time delay circuits connected in series, each said time delay circuit arranged between each pair of the sensing circuits.
9 . The non-volatile memory device of claim 1 , wherein the delay circuits within the column driver are connected in series, each said delay circuits arranged between each group including a plurality of the sensing circuits.
10 . The non-volatile memory device of claim 1 , wherein the controller includes:
a plurality of enable lines coupling the controller to each group with a plurality of the sensing circuits within the column driver, and
a plurality of time delay circuits connected in series with an identical delay value arranged between each of said enable lines such that a plurality of enable signals are sequentially sent to the groups of HV switches coupled through the enable lines, respectively.
11 . The non-volatile memory device of claim 1 , wherein the time delay circuit is configured with a plurality of a pair of inverters connected in series.
12 . The non-volatile memory device of claim 1 , the non-volatile memory cell includes:
a pair of PMOS transistors configured to share a floating gate;
a stack of three NMOS transistors, a middle of said NMOS transistor has a gate extended to the floating gate;
a plurality of word lines connected to the pair of PMOS transistors for program, write, or erase data stored in the floating gate;
a pair of lines for enabling activation of the NMOS transistors;
a bit line connected to one end of the stack of three NMOS transistors; and
a sensing line connected to the other end of the stack of three NMOS transistors for sensing currents flow via a bit line.
13 . The non-volatile memory device of claim 2 , the high voltage switch is connected to a charge pump circuit, said high voltage circuit is configured to transmit an input signal to the connected non-volatile memory cell, transmit the predefined reference voltage, two times the reference voltage, three times the reference voltage, and four times the reference voltage to the non-volatile memory cell when activated by the controller.