Program verify pairing in a multi-level cell memory device

1 . A memory device comprising:

a memory array; and

control logic, operatively coupled with the memory array, to perform operations comprising:

initiating a current loop of a program operation, the current loop comprising (a) a program phase where a plurality of memory cells associated with a selected wordline in a block of the memory array are programmed to respective ones of a plurality of programming levels and (b) a corresponding program verify phase;

identifying a first sub-set of the plurality of programming levels to be verified during the program verify phase of the current loop, the first sub-set comprising two or more dynamically selected programming levels comprising at least a lowest programming level for which at least one memory cell failed to pass the program verify phase of a previous loop and a second lowest programing level for which at least one memory cell failed to pass the program verify phase of the previous loop;

identifying memory cells of the plurality of memory cells associated with the first sub-set of the plurality of programming levels to be verified during the program verify phase;

causing a first program verify voltage to be applied to the selected wordline during the program verify phase; and

performing concurrent sensing operations on the identified memory cells of the plurality of memory cells associated with the first sub-set of the plurality programming levels to determine whether the identified memory cells were programmed to respective program verify threshold voltages corresponding to the first sub-set of the plurality of programming levels during the program phase of the current loop of the program operation.

2 . The memory device of claim 1 , wherein the control logic is to perform operations further comprising:

identifying memory cells of the plurality of memory cells associated with a second sub-set of the plurality of programming levels to be verified during the program verify phase, the second sub-set comprising two or more dynamically selected programming levels comprising at least a third lowest programming level and a fourth lowest programing level of the respective ones of the plurality of programming levels;

causing a second program verify voltage to be applied to the selected wordline during the program verify phase; and

performing concurrent sensing operations on the identified memory cells of the plurality of memory cells associated with the second sub-set of the plurality programming levels to determine whether the identified memory cells were programmed to respective program verify threshold voltages corresponding to the second sub-set of the plurality of programming levels during the program phase of the current loop of the program operation.

3 . The memory device of claim 1 , wherein the control logic is to perform operations further comprising:

determining that the plurality of memory cells comprises memory cells associated with an even number of programming levels; and

identifying one or more pairs of programming levels, each pair comprising two programming levels, and the one or more pairs together representing all of the even number of programing levels.

4 . The memory device of claim 1 , wherein the control logic is to perform operations further comprising:

determining that the plurality of memory cells comprises memory cells associated with an odd number of programming levels; and

identifying one or more pairs of programming levels, each pair comprising two programming levels, and the one or more pairs together representing all but a remaining one of the odd number of programing levels.

5 . The memory device of claim 4 , wherein the control logic is to perform operations further comprising:

performing an unpaired verify operation on one or more memory cells associated with the remaining one of the odd number of program levels.

6 . The memory device of claim 4 , wherein the control logic is to perform operations further comprising:

identifying at least one memory cell associated with a programming level that is not to be verified in the current loop of the program operation; and

performing concurrent sensing operations on the at least one memory cell associated with a programming level that is not to be verified in the current loop and on the one or more memory cells associated with the remaining one of the odd number of program levels.

7 . The memory device of claim 1 , wherein the control logic is to perform operations further comprising:

initiating one or more additional loops of the program operation, wherein, in each of the one or more additional loops, the control logic is to identify memory cells of the plurality of memory cells associated with different sub-sets of the plurality of programming levels to be verified.

8 . A method comprising:

initiating a current loop of a program operation, the current loop comprising (a) a program phase where a plurality of memory cells associated with a selected wordline in a block of a memory array of a memory device are programmed to respective ones of a plurality of programming levels and (b) a corresponding program verify phase;

identifying a first sub-set of the plurality of programming levels to be verified during the program verify phase of the current loop, the first sub-set comprising two or more dynamically selected programming levels comprising at least a lowest programming level for which at least one memory cell failed to pass the program verify phase of a previous loop and a second lowest programing level for which at least one memory cell failed to pass the program verify phase of the previous loop;

identifying memory cells of the plurality of memory cells associated with the first sub-set of the plurality of programming levels to be verified during the program verify phase;

causing a first program verify voltage to be applied to the selected wordline during the program verify phase; and

performing concurrent sensing operations on the identified memory cells of the plurality of memory cells associated with the first sub-set of the plurality programming levels to determine whether the identified memory cells were programmed to respective program verify threshold voltages corresponding to the first sub-set of the plurality of programming levels during the program phase of the current loop of the program operation.

9 . The method of claim 8 , further comprising:

identifying memory cells of the plurality of memory cells associated with a second sub-set of the plurality of programming levels to be verified during the program verify phase, the second sub-set comprising two or more dynamically selected programming levels comprising at least a third lowest programming level and a fourth lowest programing level of the respective ones of the plurality of programming levels;

causing a second program verify voltage to be applied to the selected wordline during the program verify phase; and

performing concurrent sensing operations on the identified memory cells of the plurality of memory cells associated with the second sub-set of the plurality programming levels to determine whether the identified memory cells were programmed to respective program verify threshold voltages corresponding to the second sub-set of the plurality of programming levels during the program phase of the current loop of the program operation.

10 . The method of claim 8 , further comprising:

determining that the plurality of memory cells comprises memory cells associated with an even number of programming levels; and

identifying one or more pairs of programming levels, each pair comprising two programming levels, and the one or more pairs together representing all of the even number of programing levels.

11 . The method of claim 8 , further comprising:

determining that the plurality of memory cells comprises memory cells associated with an odd number of programming levels; and

identifying one or more pairs of programming levels, each pair comprising two programming levels, and the one or more pairs together representing all but a remaining one of the odd number of programing levels.

12 . The method of claim 11 , further comprising:

performing an unpaired verify operation on one or more memory cells associated with the remaining one of the odd number of program levels.

13 . The method of claim 11 , further comprising:

identifying at least one memory cell associated with a programming level that is not to be verified in the current loop of the program operation; and

performing concurrent sensing operations on the at least one memory cell associated with a programming level that is not to be verified in the current loop and on the one or more memory cells associated with the remaining one of the odd number of program levels.

14 . The method of claim 8 , further comprising:

initiating one or more additional loops of the program operation, wherein, in each of the one or more additional loops, the control logic is to identify memory cells of the plurality of memory cells associated with different sub-sets of the plurality of programming levels to be verified.

15 . A memory device comprising:

a memory array; and

control logic, operatively coupled with the memory array to perform operations comprising:

initiating a current loop of a program operation, the current loop comprising (a) a program phase where a plurality of memory cells associated with a selected wordline in a block of the memory array are programmed to respective ones of a plurality of programming levels and (b) a corresponding program verify phase;

determining whether the plurality of memory cells comprises memory cells associated with an odd number of programming levels;

responsive to determining that the plurality of memory cells comprises memory cells associated with an odd number of programming levels, identifying one or more pairs of programming levels for which at least one memory cell failed to pass the program verify phase of a previous loop, each pair comprising two programming levels, and the one or more pairs together representing all but a remaining one of the odd number of programing levels;

associating the remaining one of the odd number of programming levels with an additional programming level; and

performing a plurality of paired verify operations during the program verify phase on memory cells associated with the one or more pairs of programming levels and on memory cells associated with the remaining one of the odd number of programming levels and the additional programming level.

16 . The memory device of claim 15 , wherein the additional programming level comprises a programming level that is not to be verified in the current loop.

17 . The memory device of claim 15 , wherein the additional programming level comprises one of the plurality of programming levels from one of the one or more pairs of programming levels.

18 . The memory device of claim 15 , wherein performing the plurality of paired verify operations comprises:

causing a first program verify voltage to be applied to the selected wordline during the program verify phase; and

performing concurrent sensing operations on the identified memory cells of the plurality of memory cells associated with the one or more pairs of programming levels and on memory cells associated with the remaining one of the odd number of programming levels and the additional programming level.

19 . The memory device of claim 15 , wherein the control logic is to perform operations further comprising:

responsive to determining that the plurality of memory cells does not comprise memory cells associated with an odd number of programming levels, identifying the one or more pairs of programming levels, each pair comprising two programming levels, and the one or more pairs together representing all of the plurality of programing levels.

20 . The memory device of claim 15 , wherein the control logic is to perform operations further comprising:

initiating one or more additional loops of the program operation, wherein, in each of the one or more additional loops, the control logic is to identify memory cells of the plurality of memory cells associated with different pairs of the plurality of programming levels to be verified.