Memories, operation methods of memories, and memory systems

1 . A memory, comprising:

a memory cell array comprising memory strings, each of the memory strings comprising a first select transistor, memory cells, and a second select transistor sequentially connected in series;

word lines coupled to the memory cells;

a first select line coupled to the first select transistor; and

a peripheral circuit coupled to the word lines and the first select line, and configured to:

in a verify period of a verify operation, apply a verify voltage to a selected word line;

in a first period of a recovery period of the verify operation, apply a first voltage to a first word line, and apply a second voltage to a second word line, wherein the second voltage is greater than the first voltage, and wherein the first voltage and the second voltage are both less than a pass voltage applied during a program operation; and

in a second period of the recovery period of the verify operation, apply a third voltage to the first select line, wherein the third voltage is greater than a threshold voltage of the first select transistor to transition the first select transistor to an on state.

2 . The memory of claim 1 , wherein the peripheral circuit is further configured to:

in a third period of the recovery period of the verify operation, apply a fourth voltage to the first word line, and apply a fifth voltage to the second word line, wherein the fifth voltage is greater than the fourth voltage.

3 . The memory of claim 1 , further comprising a second select line coupled to the second select transistor, wherein

the peripheral circuit is further configured to:

in the second period of the recovery period of the verify operation, apply a fourth voltage to the second select line.

4 . The memory of claim 3 , wherein the peripheral circuit is further configured to:

after the second period of the recovery period of the verify operation, apply a sixth voltage to the first select line, wherein the sixth voltage is less than the third voltage.

5 . The memory of claim 4 , wherein the peripheral circuit is further configured to:

in a fourth period of the recovery period of the verify operation, apply the fourth voltage to the first select line.

6 . The memory of claim 5 , wherein the peripheral circuit is further configured to:

in a fifth period of the recovery period of the verify operation, apply a program voltage to the second word line, and apply a pass voltage to the first word line.

7 . The memory of claim 1 , wherein the peripheral circuit is further configured to:

in the first period of the recovery period of the verify operation, apply a fourth voltage to a third word line, wherein the third word line is located between the second word line and the first select line.

8 . The memory of claim 7 , wherein a memory cell coupled with the first word line is a programmed memory cell, and a memory cell coupled with the third word line is an unprogrammed memory cell.

9 . The memory of claim 8 , wherein the peripheral circuit is further configured to:

in the second period of the recovery period of the verify operation, apply a seventh voltage to a source line, wherein the first select line is located between the third word line and the source line.

10 . The memory of claim 8 , wherein the peripheral circuit is further configured to:

in the second period of the recovery period of the verify operation, apply an eighth voltage to a bit line, wherein the first select line is located between the third word line and the bit line.

11 . The memory of claim 1 , wherein the peripheral circuit is further configured to:

in the first period of the recovery period of the verify operation, apply the second voltage to a fourth word line, wherein the fourth word line is located between the second word line and the first word line.

12 . The memory of claim 1 , wherein the peripheral circuit is further configured to:

in the first period of the recovery period of the verify operation, apply a fourth voltage to a fifth word line, wherein the fifth word line is located between the first word line and a second select line.

13 . The memory of claim 1 , wherein the peripheral circuit is further configured to:

in a first period of a recovery period of a last verify operation on the memory string, apply a ninth voltage to the first word line and the second word line.

14 . The memory of claim 1 , wherein the second voltage is less than a pass voltage.

15 . A method of operating a memory, comprising:

in a verify period of a verify operation, apply a verify voltage to a selected word line;

in a first period of a recovery period of the verify operation, applying a first voltage to a first word line, and applying a second voltage to a second word line, wherein the second voltage is greater than the first voltage, and wherein the first voltage and the second voltage are both less than a pass voltage applied during a program operation; and

in a second period of the recovery period of the verify operation, applying a third voltage to a first select line, wherein the third voltage is greater than a threshold voltage of a first select transistor to transition the first select transistor to an on state.

16 . The method of claim 15 , further comprising:

in a third period of the recovery period of the verify operation, applying a fourth voltage to the first word line, and applying a fifth voltage to the second word line, wherein the fifth voltage is greater than the fourth voltage.

17 . The method of claim 15 , further comprising:

in the second period of the recovery period of the verify operation, applying a fourth voltage to a second select line.

18 . The method of claim 17 , further comprising:

after the second period of the recovery period of the verify operation, applying a sixth voltage to the first select line, wherein the sixth voltage is less than the third voltage.

19 . The method of claim 18 , further comprising:

in a fourth period of the recovery period of the verify operation, applying the fourth voltage to the first select line.

20 . A memory system, comprising:

one or more memories, comprising:

a memory cell array comprising memory strings, each of the memory strings comprising a first select transistor, memory cells, and a second select transistor sequentially connected in series;

word lines coupled to the memory cells;

a first select line coupled to the first select transistor; and

a peripheral circuit coupled to the word lines and the first select line, and configured to:

in a verify period of a verify operation, apply a verify voltage to a selected word line;

in a first period of a recovery period of the verify operation, apply a first voltage to a first word line, and apply a second voltage to a second word line, wherein the second voltage is greater than the first voltage, and wherein the first voltage and the second voltage are both less than a pass voltage applied during a program operation; and

in a second period of the recovery period of the verify operation, apply a third voltage to the first select line, wherein the third voltage is greater than a threshold voltage of the first select transistor to transition the first select transistor to an on state; and

a memory controller coupled to the one or more memories and configured to control the one or more memories.