Memory devices, program methods, and memory systems

1 . A memory device, comprising:

a memory cell array including a plurality of memory cells and a word line coupled with the plurality of memory cells, wherein each memory cell of the plurality of memory cells is configured to be in one of a plurality of data states; and

a peripheral circuit coupled with the memory cell array and configured to:

apply a verify voltage to the word line when incremental step pulse programming is performed on the plurality of memory cells, further including to:

perform a first verify operation on a first data state among the plurality of data states; and

perform a second verify operation on a second data state among the plurality of data states, wherein the first data state is adjacent to the second data state, and a distance between a first expected threshold voltage distribution corresponding to the first data state and a second expected threshold voltage distribution corresponding to the second data state is greater than a preset threshold;

divide, according to a verification result, memory cells that are expected to be programmed to the second data state among the plurality of memory cells into a first group and a second group, wherein the memory cells included in the first group are programmed to the second data state earlier than the memory cells included in the second group; and

apply a first program pulse to the word line after the verification of the first data state is passed to continue programming on the memory cells that are expected to be programmed to the second data state, wherein the first program pulse is a sum of a second program pulse and a preset bias offset voltage, and the second program pulse is a previous program pulse of the first program pulse.

2 . The memory device of claim 1 , wherein the peripheral circuit is further configured to:

determine the verification result of the second verify operation after the verification of the first data state is passed;

divide, according to the verification result, the memory cells that are expected to be programmed to the second data state among the plurality of memory cells into a plurality of groups; and

apply different bit line voltages to bit lines coupled with different groups of memory cells among the plurality of groups of the memory cells when the memory cells that are expected to be programmed to the second data state among the plurality of memory cells are continuously programmed.

3 . The memory device of claim 2 , wherein the peripheral circuit is further configured to,

when the memory cells that are expected to be programmed to the second data state among the plurality of memory cells are continuously programmed, apply a first bit line voltage to a bit line coupled with the memory cells included in the first group, and apply a second bit line voltage to a bit line coupled with the memory cells included in the second group, wherein the first bit line voltage is greater than the second bit line voltage.

4 . The memory device of claim 1 , wherein the peripheral circuit is further configured to, after the application of the first program pulse and when the verification of the second data state is not passed, continuously apply a gradually increasing program pulse to the word line coupled with the plurality of memory cells step by step based on the first program pulse and by taking a step incremental voltage as a step size, wherein the application of the gradually increasing program pulse continues until the verification of a last data state among the plurality of data states is passed, wherein the step incremental voltage is less than the preset bias offset voltage.

5 . The memory device of claim 4 , wherein the last data state among the plurality of data states includes the second data state.

6 . The memory device of claim 1 , wherein the peripheral circuit is further configured to program each of the plurality of memory cells from one of the plurality of data states to a corresponding target data state among a plurality of target data states.

7 . The memory device of claim 6 , wherein the plurality of data states include a data state P 0 , a data state P 1 , a data state P 2 , and a data state P 3 with sequentially increasing voltage values included in the first and second expected threshold voltage distributions, wherein the first data state includes the data state P 2 , and the second data state includes the data state P 3 .

8 . The memory device of claim 7 , wherein the plurality of data states include 16 target data states, wherein each of the plurality of data states is configured to correspond to 4 target data states.

9 . The memory device of claim 1 , wherein the peripheral circuit is further configured to:

record a number of times for applying the first program pulse and the second program pulse to the word line coupled with the plurality of memory cells for the first program pulse and the second program pulse; and

when the number of times for applying the first program pulse and the second program pulse is equal to a preset number of times, apply the verify voltage to the word line, wherein the verify voltage is applied to perform the first verify operation and the second verify operation on the first data state and the second data state among the plurality of data states simultaneously.

10 . The memory device of claim 1 , wherein the preset bias offset voltage is positively correlated with the distance between the first expected threshold voltage distribution and the second expected threshold voltage distribution, wherein the greater the distance, the greater the preset bias offset voltage.

11 . A program method of a memory device, wherein the memory device includes a plurality of memory cells and a word line coupled with the plurality of memory cells, wherein each memory cell is configured to be in one of a plurality of data states, and the program method comprises:

applying a verify voltage to the word line when incremental step pulse programming is performed on the plurality of memory cells, further including:

performing a first verify operation on a first data state among the plurality of data states; and

performing a second verify operation on a second data state among the plurality of data states, wherein the first data state is adjacent to the second data state, and a distance between a first expected threshold voltage distribution corresponding to the first data state and a second expected threshold voltage distribution corresponding to the second data state is greater than a preset threshold;

dividing, according to a verification result, memory cells that are expected to be programmed to the second data state among the plurality of memory cells into a first group and a second group, wherein the memory cells included in the first group are programmed to the second data state earlier than the memory cells included in the second group; and

applying a first program pulse to the word line after the verification of the first data state is passed to continue programming on the memory cells that are expected to be programmed to the second data state among the plurality of memory cells, wherein the first program pulse is a sum of a second program pulse and a preset bias offset voltage, and the second program pulse is a previous program pulse of the first program pulse.

12 . The program method of claim 11 , further including:

determining the verification result of the second verify operation after the verification of the first data state is passed;

dividing, according to the verification result, the memory cells that are expected to be programmed to the second data state among the plurality of memory cells into a plurality of groups; and

applying different bit line voltages to bit lines coupled with different groups of memory cells among the plurality of groups of the memory cells when the memory cells that are expected to be programmed to the second data state among the plurality of memory cells are continuously programmed.

13 . The program method of claim 12 , wherein:

applying the different bit line voltages to bit lines coupled with the different groups of the memory cells among the plurality of groups of the memory cells when the memory cells that are expected to be programmed to the second data state among the plurality of memory cells are continuously programmed further includes, when the memory cells that are expected to be programmed to the second data state among the plurality of memory cells are continuously programmed, applying a first bit line voltage to a bit line coupled with the memory cells included in the first group, and applying a second bit line voltage to a bit line coupled with the memory cells included in the second group, wherein the first bit line voltage is greater than the second bit line voltage.

14 . The program method of claim 11 , further including, after the application of the first program pulse and when the verification of the second data state is not passed, continuously applying a gradually increasing program pulse to the word line coupled with the plurality of memory cells step by step based on the first program pulse and by taking a step incremental voltage as a step size, wherein the application of the gradually increasing programing pulse continues until the verification of a last data state among the plurality of data states is passed, wherein the step incremental voltage is less than the preset bias offset voltage.

15 . The program method of claim 14 , wherein the last data state among the plurality of data states includes the second data state.

16 . The program method of claim 11 , further including programming each of the plurality of memory cells from one of the plurality of data states to a corresponding target data state among a plurality of target data states.

17 . The program method of claim 16 , wherein the plurality of data states include a data state P 0 , a data state P 1 , a data state P 2 , and a data state P 3 with sequentially increasing voltage values included in the first and second expected threshold voltage distributions, wherein the first data state includes the data state P 2 , and the second data state includes the data state P 3 .

18 . The program method of claim 17 , wherein the plurality of data states include 16 target data states, wherein each of the plurality of data states is configured to correspond to 4 target data states.

19 . The program method of claim 11 , further including:

recording a number of times for applying the first program pulse and the second program pulse to the word line coupled with the plurality of memory cells for the first program pulse and the second program pulse; and

when the number of times for applying the first program pulse and the second program pulse is equal to a preset number of times, applying the verify voltage to the word line, wherein the verify voltage is applied to perform the first verify operation and the second verify operation on the first data state and the second data state among the plurality of data states simultaneously.

20 . A memory system, comprising:

one or more memory devices, each of the memory devices includes:

a memory cell array including a plurality of memory cells and a word line coupled with the plurality of memory cells, wherein each of the memory cell of the plurality of memory cells is configured to be in one of a plurality of data states; and

a peripheral circuit coupled with the memory cell array and configured to:

apply a verify voltage to the word line when incremental step pulse programming is performed on the plurality of memory cells, further including to:

perform a first verify operation on a first data state among the plurality of data states; and

perform a second verify operation on a second data state among the plurality of data states, wherein the first data state is adjacent to the second data state, and a distance between a first expected threshold voltage distribution corresponding to the first data state and a second expected threshold voltage distribution corresponding to the second data state is greater than a preset threshold;

divide, according to a verification result, memory cells that are expected to be programmed to the second data state among the plurality of memory cells into a first group and a second group, wherein the memory cells included in the first group are programmed to the second data state earlier than the memory cells included in the second group; and

apply a first program pulse to the word line after the verification of the first data state is passed to continue programming on the memory cells that are expected to be programmed to the second data state, wherein the first program pulse is a sum of a second program pulse and a preset bias offset voltage, and the second program pulse is a previous program pulse of the first program pulse; and

a memory controller coupled with the one or more memory devices and configured to control the one or more memory devices.