Dual word line all-string preprogram for lateral data retention improvement

1 . A memory apparatus, comprising:

memory cells each connected to one of a plurality of word lines and configured to retain a threshold voltage corresponding to one of a plurality of data states, the memory cells disposed in memory holes extending vertically through a stack of the plurality of word lines; and

a control means configured to:

apply a pre-programming pulse of a pre-program voltage to a selected one and at least one neighboring one of the plurality of word lines in a pre-program operation, the at least one neighboring one of the plurality of word lines including a first neighboring word line disposed immediately adjacent to and vertically above the selected one of the plurality of word lines in the stack, and

apply each of a series of programming pulses of a program voltage followed by verification pulses of a plurality of program verify voltages each associated with one of the plurality of data states to the selected one of the plurality of word lines to program and verify the memory cells connected thereto during each of a plurality of program loops of a program operation.

2 . The memory apparatus as set forth in claim 1 , wherein the plurality of word lines and a plurality of dielectric layers extend horizontally and overlay one another in an alternating fashion in the stack, the memory cells are connected in series between a drain-side select gate transistor on a drain-side of each of the memory holes and a source-side select gate transistor on a source-side of each of the memory holes, the drain-side select gate transistor of each of the memory holes is connected to one of a plurality of bit lines and the source-side select gate transistor of each of the memory holes is connected to a source line.

3 . The memory apparatus as set forth in claim 1 , wherein the at least one neighboring one of the plurality of word lines further includes a second neighboring word line disposed immediately adjacent to and vertically above the first neighboring word line in the stack.

4 . The memory apparatus as set forth in claim 1 , wherein the memory holes are organized in rows grouped in a plurality of strings and the control means is further configured, prior to programming the memory cells of a first one of the plurality of strings, to apply the pre-programming pulse of the pre-program voltage to the selected one and the at least one neighboring one of the plurality of word lines coupled to the memory cells of all of the plurality of strings simultaneously in the pre-program operation.

5 . The memory apparatus as set forth in claim 1 , wherein the memory holes are organized in rows grouped in a plurality of strings, the selected one of the plurality of word lines includes a first selected one of the plurality of word lines and a second selected one of the plurality of word lines and subsequent selected ones of the plurality of word lines, the at least one neighboring one of the plurality of word lines includes a second neighboring word line disposed immediately adjacent to and vertically above the second selected one of the plurality of word lines in the stack and subsequent neighboring word lines each disposed immediately adjacent to and vertically above each of the subsequent selected ones of the plurality of word lines, the plurality of strings comprise one of a plurality of blocks and include a first one of the plurality of strings and subsequent ones of the plurality of strings, and the control means is further configured to:

erase the one of the plurality of blocks in an erase operation;

start a block program of the one of the plurality of blocks;

apply the pre-programming pulse of the pre-program voltage to the first selected one of the plurality of word lines and the first neighboring word line in the pre-program operation;

program and verify the memory cells of the first one of the plurality of strings connected to the first selected one of the plurality of word lines in the program operation;

program and verify the memory cells of each of the subsequent ones of the plurality of strings connected to the first selected one of the plurality of word lines in the program operation;

program and verify the memory cells of the first one of the plurality of strings connected to the second selected one of the plurality of word lines in the program operation;

program and verify the memory cells of each of the subsequent ones of the plurality of strings connected to the second selected one of the plurality of word lines in the program operation;

apply the pre-programming pulse of the pre-program voltage to one of the subsequent selected ones of the plurality of word lines and one of the subsequent neighboring word lines in the pre-program operation;

program and verify the memory cells of the first one of the plurality of strings connected to the one of the subsequent selected ones of the plurality of word lines in the program operation;

program and verify the memory cells of each of the subsequent ones of the plurality of strings connected to the one of the subsequent selected ones of the plurality of word lines in the program operation; and

end the block program of the one of the plurality of blocks.

6 . The memory apparatus as set forth in claim 5 , wherein, following programming and verifying the memory cells of each of the subsequent ones of the plurality of strings connected to the first selected one of the plurality of word lines in the program operation, the control means is further configured to apply the pre-programming pulse of the pre-program voltage to the second selected one of the plurality of word lines and the second neighboring word line in the pre-program operation.

7 . The memory apparatus as set forth in claim 1 , wherein the pre-program voltage includes a selected pre-program voltage and a neighbor pre-program voltage, the selected pre-program voltage and the neighbor pre-program voltage are different in magnitude from one another, and the control means is further configured to:

apply the pre-programming pulse of the selected pre-program voltage to the selected one of the plurality of word lines in the pre-program operation; and

apply the pre-programming pulse of the neighbor pre-program voltage to the at least one neighboring one of the plurality of word lines in the pre-program operation.

8 . A controller in communication with a memory apparatus including memory cells each connected to one of a plurality of word lines and configured to retain a threshold voltage corresponding to one of a plurality of data states, the memory cells disposed in memory holes extending vertically through a stack of the plurality of word lines, the controller configured to:

instruct the memory apparatus to apply a pre-programming pulse of a pre-program voltage to a selected one and at least one neighboring one of the plurality of word lines in a pre-program operation, the at least one neighboring one of the plurality of word lines including a first neighboring word line disposed immediately adjacent to and vertically above the selected one of the plurality of word lines in the stack; and

instruct the memory apparatus to apply each of a series of programming pulses of a program voltage followed by verification pulses of a plurality of program verify voltages each associated with one of the plurality of data states to the selected one of the plurality of word lines to program and verify the memory cells connected thereto during each of a plurality of program loops of a program operation.

9 . The controller as set forth in claim 8 , wherein the plurality of word lines and a plurality of dielectric layers extend horizontally and overlay one another in an alternating fashion in the stack, the memory cells are connected in series between a drain-side select gate transistor on a drain-side of each of the memory holes and a source-side select gate transistor on a source-side of each of the memory holes, the drain-side select gate transistor of each of the memory holes is connected to one of a plurality of bit lines and the source-side select gate transistor of each of the memory holes is connected to a source line.

10 . The controller as set forth in claim 8 , wherein the at least one neighboring one of the plurality of word lines further includes a second neighboring word line disposed immediately adjacent to and vertically above the first neighboring word line in the stack.

11 . The controller as set forth in claim 8 , wherein the memory holes are organized in rows grouped in a plurality of strings and the controller is further configured, prior to instructing the memory apparatus to program the memory cells of a first one of the plurality of strings, to instruct the memory apparatus to apply the pre-programming pulse of the pre-program voltage to the selected one and the at least one neighboring one of the plurality of word lines coupled to the memory cells of all of the plurality of strings simultaneously in the pre-program operation.

12 . The controller as set forth in claim 8 , wherein the memory holes are organized in rows grouped in a plurality of strings, the selected one of the plurality of word lines includes a first selected one of the plurality of word lines and a second selected one of the plurality of word lines and subsequent selected ones of the plurality of word lines, the at least one neighboring one of the plurality of word lines includes a second neighboring word line disposed immediately adjacent to and vertically above the second selected one of the plurality of word lines in the stack and subsequent neighboring word lines each disposed immediately adjacent to and vertically above each of the subsequent selected ones of the plurality of word lines, the plurality of strings comprise one of a plurality of blocks and include a first one of the plurality of strings and subsequent ones of the plurality of strings, and the controller is further configured to:

instruct the memory apparatus to erase the one of the plurality of blocks in an erase operation;

start a block program of the one of the plurality of blocks;

instruct the memory apparatus to apply the pre-programming pulse of the pre-program voltage to the first selected one of the plurality of word lines and the first neighboring word line in the pre-program operation;

instruct the memory apparatus to program and verify the memory cells of the first one of the plurality of strings connected to the first selected one of the plurality of word lines in the program operation;

instruct the memory apparatus to program and verify the memory cells of each of the subsequent ones of the plurality of strings connected to the first selected one of the plurality of word lines in the program operation;

instruct the memory apparatus to program and verify the memory cells of the first one of the plurality of strings connected to the second selected one of the plurality of word lines in the program operation;

instruct the memory apparatus to program and verify the memory cells of each of the subsequent ones of the plurality of strings connected to the second selected one of the plurality of word lines in the program operation;

instruct the memory apparatus to apply the pre-programming pulse of the pre-program voltage to one of the subsequent selected ones of the plurality of word lines and one of the subsequent neighboring word lines in the pre-program operation;

instruct the memory apparatus to program and verify the memory cells of the first one of the plurality of strings connected to the one of the subsequent selected ones of the plurality of word lines in the program operation;

instruct the memory apparatus to program and verify the memory cells of each of the subsequent ones of the plurality of strings connected to the one of the subsequent selected ones of the plurality of word lines in the program operation; and

end the block program of the one of the plurality of blocks.

13 . The controller as set forth in claim 8 , wherein the controller is further configured to instruct the memory apparatus to employ the pre-program operation only when programming the memory cells of specific predetermined ones of the plurality of word lines and instruct the memory apparatus to not employ the pre-program operation when programming the memory cells of others of the plurality of word lines besides the specific predetermined ones of the plurality of word lines.

14 . A method of operating a memory apparatus including memory cells each connected to one of a plurality of word lines and configured to retain a threshold voltage corresponding to one of a plurality of data states, the memory cells disposed in memory holes extending vertically through a stack of the plurality of word lines, the method comprising the steps of:

applying a pre-programming pulse of a pre-program voltage to a selected one and at least one neighboring one of the plurality of word lines in a pre-program operation, the at least one neighboring one of the plurality of word lines including a first neighboring word line disposed immediately adjacent to and vertically above the selected one of the plurality of word lines in the stack; and

applying each of a series of programming pulses of a program voltage followed by verification pulses of a plurality of program verify voltages each associated with one of the plurality of data states to the selected one of the plurality of word lines to program and verify the memory cells connected thereto during each of a plurality of program loops of a program operation.

15 . The method as set forth in claim 14 , wherein the plurality of word lines and a plurality of dielectric layers extend horizontally and overlay one another in an alternating fashion in the stack, the memory cells are connected in series between a drain-side select gate transistor on a drain-side of each of the memory holes and a source-side select gate transistor on a source-side of each of the memory holes, the drain-side select gate transistor of each of the memory holes is connected to one of a plurality of bit lines and the source-side select gate transistor of each of the memory holes is connected to a source line.

16 . The method as set forth in claim 14 , wherein the at least one neighboring one of the plurality of word lines further includes a second neighboring word line disposed immediately adjacent to and vertically above the first neighboring word line in the stack.

17 . The method as set forth in claim 14 , wherein the memory holes are organized in rows grouped in a plurality of strings and the method further includes the step of prior to programming the memory cells of a first one of the plurality of strings, applying the pre-programming pulse of the pre-program voltage to the selected one and the at least one neighboring one of the plurality of word lines coupled to the memory cells of all of the plurality of strings simultaneously in the pre-program operation.

18 . The method as set forth in claim 14 , wherein the memory holes are organized in rows grouped in a plurality of strings, the selected one of the plurality of word lines includes a first selected one of the plurality of word lines and a second selected one of the plurality of word lines and subsequent selected ones of the plurality of word lines, the at least one neighboring one of the plurality of word lines includes a second neighboring word line disposed immediately adjacent to and vertically above the second selected one of the plurality of word lines in the stack and subsequent neighboring word lines each disposed immediately adjacent to and vertically above each of the subsequent selected ones of the plurality of word lines, the plurality of strings comprise one of a plurality of blocks and include a first one of the plurality of strings and subsequent ones of the plurality of strings, and the method further includes the steps of

erasing the one of the plurality of blocks in an erase operation;

starting a block program of the one of the plurality of blocks;

applying the pre-programming pulse of the pre-program voltage to the first selected one of the plurality of word lines and the first neighboring word line in the pre-program operation;

programming and verifying the memory cells of the first one of the plurality of strings connected to the first selected one of the plurality of word lines in the program operation;

programming and verifying the memory cells of each of the subsequent ones of the plurality of strings connected to the first selected one of the plurality of word lines in the program operation;

programming and verifying the memory cells of the first one of the plurality of strings connected to the second selected one of the plurality of word lines in the program operation;

programming and verifying the memory cells of each of the subsequent ones of the plurality of strings connected to the second selected one of the plurality of word lines in the program operation;

applying the pre-programming pulse of the pre-program voltage to one of the subsequent selected ones of the plurality of word lines and one of the subsequent neighboring word lines in the pre-program operation;

programming and verifying the memory cells of the first one of the plurality of strings connected to the one of the subsequent selected ones of the plurality of word lines in the program operation;

programming and verifying the memory cells of each of the subsequent ones of the plurality of strings connected to the one of the subsequent selected ones of the plurality of word lines in the program operation; and

ending the block program of the one of the plurality of blocks.

19 . The method as set forth in claim 18 , wherein, following programming and verifying the memory cells of each of the subsequent ones of the plurality of strings connected to the first selected one of the plurality of word lines in the program operation, the method further includes the step of applying the pre-programming pulse of the pre-program voltage to the second selected one of the plurality of word lines and the second neighboring word line in the pre-program operation.

20 . The method as set forth in claim 14 , wherein the pre-program voltage includes a selected pre-program voltage and a neighbor pre-program voltage, the selected pre-program voltage and the neighbor pre-program voltage are different in magnitude from one another, and the method further includes the steps of:

applying the pre-programming pulse of the selected pre-program voltage to the selected one of the plurality of word lines in the pre-program operation; and

applying the pre-programming pulse of the neighbor pre-program voltage to the at least one neighboring one of the plurality of word lines in the pre-program operation.