Detecting extrinsic bitline defects

1 . A system comprising:

a set of memory components of a memory sub-system; and

at least one processing device operatively coupled to the set of memory components, the at least one processing device being configured to perform operations comprising:

storing a set of data in the set of memory components;

performing a set of memory operations for detecting an empty page in a portion of the set of memory components;

determining, based on performing the set of memory operations, that the portion of the set of memory components is associated with an extrinsic bitline defect; and

in response to determining that the portion of the set of memory components is associated with the extrinsic bitline defect, preventing write operations to the portion of the set of memory components.

2 . The system of claim 1 , the operations comprising marking the portion of the set of memory components as a bad block.

3 . The system of claim 1 , wherein the extrinsic bitline defect corresponds to an open bitline or a stuck bitline that prevents the portion of the set of memory components from being placed into an erased state.

4 . The system of claim 1 , wherein the extrinsic bitline defect causes undesired charge gain in the portion of the set of memory components.

5 . The system of claim 1 , wherein the extrinsic bitline defect causes a high reliability error rate (HRER) to be introduced in the portion of the set of memory components.

6 . The system of claim 5 , wherein the HRER is associated with uncorrectable errors in the set of data stored in the portion of the set of memory components.

7 . The system of claim 1 , wherein the set of memory operations includes a NAND detect empty page (NDEP) operation.

8 . The system of claim 7 , wherein the NDEP operation reads a block of data to detect charge gain and refreshes the block of data.

9 . The system of claim 1 , the operations comprising:

accessing configuration information associated with the set of memory components;

processing the configuration information to identify a plurality of portions of the set of memory components that are associated with a certain likelihood of having extrinsic bitline defects; and

storing a counter in association with the plurality of portions to represent frequency of performing the set of memory operations on the plurality of portions of the set of memory components.

10 . The system of claim 9 , the operations comprising:

determining that the portion of the set of memory components is included in the plurality of portions of the set of memory components that are associated with the certain likelihood of having extrinsic bitline defects.

11 . The system of claim 10 , the operations comprising:

setting a time period in association with updating the counter; and

incrementing the counter each time an individual memory operation of the set of memory operations is performed in relation to the plurality of portions of the set of memory components within the time period.

12 . The system of claim 11 , wherein the counter is reset when the time period expires.

13 . The system of claim 11 , the operations comprising:

determining that the counter transgresses a threshold value before expiration of the time period; and

in response to determining that the counter transgresses the threshold value, storing a flag in association with the plurality of portions, the flag corresponding to an instruction to perform an additional one of the set of memory operations after erasing an individual portion of the plurality of portions.

14 . The system of claim 13 , the operations comprising:

after performing an individual memory operation of the set of memory operations on the portion of the set of portions, determining that the portion is associated with the counter that transgresses the threshold value;

in response to determining that the portion is associated with the counter that transgresses the threshold value, performing the additional one of the set of memory operations after erasing the portion of the plurality of portions; and

computing an error rate associated with performing the additional one of the set of memory operations on the portion of the set of memory components.

15 . The system of claim 14 , the operations comprising:

determining that the error rate transgresses a maximum error rate threshold; and

in response to determining that the error rate transgresses the maximum error rate threshold, marking the portion as a bad portion to prevent the write operations to the portion of the set of memory components.

16 . The system of claim 9 , wherein the plurality of portions correspond to a first bin, wherein the counter is a first counter, and the operations comprising:

associating the first bin with the first counter;

identifying, based on the configuration information, a second bin of a second plurality of portions of the set of memory components that is associated with the certain likelihood of having extrinsic bitline defects; and

associating the second bin with a second counter to represent frequency of performing the set of memory operations on the second plurality of portions of the set of memory components of the second bin.

17 . The system of claim 1 , the operations comprising:

a set of registers for storing addresses in which the set of memory operations have been performed within a specified time period;

determining that an individual address corresponding to the portion of the set of memory components is duplicated in the set of registers;

in response to determining that the individual address corresponding to the portion of the set of memory components is duplicated in the set of registers, performing an additional one of the set of memory operations after erasing the portion of the set of memory components; and

computing an error rate associated with performing the additional one of the set of memory operations on the portion of the set of memory components.

18 . The system of claim 17 , the operations comprising:

determining that the error rate transgresses a maximum error rate threshold; and

in response to determining that the error rate transgresses the maximum error rate threshold, marking the portion as a bad portion to prevent the write operations to the portion of the set of memory components.

19 . A method comprising:

storing a set of data in a set of memory components;

performing a set of memory operations for detecting an empty page in a portion of the set of memory components;

determining, based on performing the set of memory operations, that the portion of the set of memory components is associated with an extrinsic bitline defect; and

in response to determining that the portion of the set of memory components is associated with the extrinsic bitline defect, preventing write operations to the portion of the set of memory components.

20 . A non-transitory computer-readable storage medium comprising instructions that, when executed by at least one processing device, cause the at least one processing device to perform operations comprising:

storing a set of data in a set of memory components;

performing a set of memory operations for detecting an empty page in a portion of the set of memory components;

determining, based on performing the set of memory operations, that the portion of the set of memory components is associated with an extrinsic bitline defect; and

in response to determining that the portion of the set of memory components is associated with the extrinsic bitline defect, preventing write operations to the portion of the set of memory components.