Semiconductor device with advanced pad structure and method for forming same
A method of forming a semiconductor device according to the present disclosure includes forming a metal-insulator-metal (MIM) structure in a substrate and forming an interconnect structure over the substrate. The MIM structure includes first electrodes of a first polarity and second electrodes of a second polarity. The interconnect structure includes conductive paths electrically connecting to the first and second electrodes. The conductive paths are isolated from each other inside the interconnect structure. The method also includes forming first and second contact pads over the interconnect structure. The first contact pad electrically connects a first portion of the conductive paths corresponding to the first electrodes. The second contact pad electrically connects a second portion of the conductive paths corresponding to the second electrodes.
1 . A method, comprising:
forming a metal-insulator-metal (MIM) structure in a substrate, wherein the MIM structure includes a plurality of first electrodes of a first polarity and a plurality of second electrodes of a second polarity;
forming first and second through vias on opposing sides of the MIM structure, wherein bottom surfaces of the first and second through vias are below a bottommost surface of the MIM structure;
after the forming of the first and second through vias, forming an interconnect structure over the substrate, wherein the interconnect structure includes conductive paths electrically connecting to the first and second electrodes, wherein the conductive paths are isolated from each other inside the interconnect structure; and
forming first and second contact pads over the interconnect structure, wherein the first contact pad electrically connects a first portion of the conductive paths corresponding to the first electrodes, and the second contact pad electrically connects a second portion of the conductive paths corresponding to the second electrodes.
2 . The method of claim 1 , wherein the MIM structure is a deep trench capacitor (DTC).
3 . The method of claim 1 , wherein the forming of the MIM structure includes:
etching the substrate to form at least first and second trenches;
depositing a stack of conductive layers and dielectric layers alternatively arranged in the first and second trenches; and
patterning the stack to form the MIM structure.
4 . The method of claim 3 , wherein in a cross-sectional view the second contact pad extends in a way such that the second trench is fully under the second contact pad, and at least a center portion of the first trench is positioned directly under a gap between the first and second contact pads.
5 . The method of claim 1 , further comprising:
depositing first and second passivation layers over the interconnect structure, wherein each of the first and second contact pads includes a plurality of lower portions surrounded by the first passivation layer and an upper portion surrounded by the second passivation layer and contacting each of the lower portions.
6 . The method of claim 5 , wherein each of the lower portions electrically connects one of the conductive paths in the interconnect structure.
7 . The method of claim 5 , wherein the lower portions and the upper portion include different conductive materials.
8 . The method of claim 7 , wherein the upper portion includes aluminum.
9 . The method of claim 1 , wherein the first and second contact pads are aluminum-containing pads.
10 . The method of claim 1 ,
wherein after the forming of the first and second contact pads, the first contact pad electrically connects the first through via to the first electrodes, the second contact pad electrically connects the second through via to the second electrodes, and the first and second through vias remain electrically isolated from the first and second electrodes within the interconnect structure.
11 . A method of manufacturing a capacitor, comprising:
forming a trench in a substrate;
depositing a stack of alternating metal layers and dielectric layers in the trench;
depositing a dielectric layer over the stack;
forming conductive vias extending through the dielectric layer and contacting the metal layers;
forming one or more metallization layers over the dielectric layer, wherein the conductive vias remain electrically isolated from each other through the metallization layers;
forming a first passivation layer over the metallization layers;
forming contact pads with lower portions embedded in the passivation layer, wherein each of the contact pads electrically connects two or more of the conductive vias; and
forming a second passivation layer over the first passivation layer, wherein upper portions of the contact pads are surrounded by the second passivation layer.
12 . The method of claim 11 , wherein in a top view at least one of the contact pads includes a via pad connected to a trace, and the via pad has a width larger than the trace.
13 . The method of claim 12 , wherein the trace has a straight portion extending from the via pad and a bended portion connected to the straight portion.
14 . The method of claim 11 , wherein the contact pads include an aluminum alloy.
15 . The method of claim 11 , further comprising:
forming through substrate vias (TSVs) extending through the substrate, wherein the TSVs are electrically connected to the conductive vias through the contact pads.
16 . The method of claim 15 , further comprising:
forming backside contact pads on a backside surface of the substrate, wherein the backside contact pads are electrically connected to the conductive vias through the TSVs and the contact pads.
17 . The method of claim 16 , wherein the contact pads are Al—Cu pads, and the backside contact pads are NiPdAu—Cu pads.
18 . A method, comprising:
etching a substrate to form at least first and second trenches;
depositing a stack of metal layers and dielectric layers alternatively arranged in the first and second trenches;
patterning the stack to form a deep trench capacitor (DTC) that includes a plurality of first electrodes of a first polarity and a plurality of second electrodes of a second polarity;
forming an interconnect structure over the substrate, wherein the interconnect structure includes conductive paths electrically connecting to the first and second electrodes, wherein the conductive paths are isolated from each other inside the interconnect structure;
forming first and second contact pads over the interconnect structure, wherein the first contact pad electrically connects a first portion of the conductive paths associated with the first electrodes, and the second contact pad electrically connects a second portion of the conductive paths associated with the second electrodes, wherein in a cross-sectional view the second contact pad extends in a way such that the second trench is fully under the second contact pad, and at least a center portion of the first trench is positioned directly under a gap between the first and second contact pads; and
depositing first and second passivation layers over the interconnect structure, wherein each of the first and second contact pads includes a plurality of lower portions surrounded by the first passivation layer and an upper portion surrounded by the second passivation layer and contacting each of the lower portions.
19 . The method of claim 18 , wherein the first and second contact pads include aluminum alloy.
20 . The method of claim 18 , further comprising:
forming first and second through substrate vias (TSVs) extending through the substrate, wherein the first and second TSVs are electrically connected to the first and second contact pads, respectively; and
forming first and second backside contact pads on a backside surface of the substrate, wherein the first and second backside contact pads are electrically connected to the first and second contact pads through the first and second TSVs, respectively.