IP Library Granted Patent US 12706363
Granted Patent B2
US 12706363 · App. 18/691,845 · Granted Aug 11, 2026

High-frequency line connection structure

Inventor: Hiromasa Tanobe (Tokyo, JP)
Assignee: NTT, INC.
H01P3/06H01P3/081H01P3/16
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Quick Facts
Patent No.
US 12706363
App. No.
18/691,845
Granted
Aug 11, 2026
Kind
B2
Abstract

A high-frequency line connecting structure includes microstrip lines, and a connecting part which bends an extension direction of the line at a place where the microstrip lines are connected. Spaces from which the substrate is removed are formed on the inner peripheral side and the outer peripheral side of the connecting part. The total volume of the space on the inner peripheral side is smaller than the total volume of the space on the outer peripheral side.

Claims (49)

1 . A structure comprising:

a substrate comprising a multilayer structure including a first plurality of layers, the first plurality of layers being stacked perpendicular to a surface of the substrate, each of the first plurality of layers being made of an insulator or a semi-insulating semiconductor;

a first high-frequency line disposed in the substrate, the first high-frequency line being disposed in a first layer of the first plurality of layers;

a second high-frequency line disposed in the substrate, the second high-frequency line having an extension direction different from an extension direction of the first high-frequency line, the second high-frequency line extending through the first plurality of layers; and

a connecting part connecting the first high-frequency line to the second high-frequency line and comprising a bend in an extension direction of the connecting part,

wherein the substrate defines N first spaces on an outer peripheral side of the connecting part, and M second spaces on an inner peripheral side of the connecting part,

wherein the N first spaces and the M second spaces are formed by removing a part of the substrate,

wherein M and N are each an integer of 1 or more,

wherein a relationship MEN is satisfied, and

wherein the N first spaces and the M second spaces expose a ground plane or are disposed at a position adjacent to the ground plane, the ground plane being disposed in the substrate around at least one of the first high-frequency line or the second high-frequency line, and the ground plane is configured to function as a capacitive adjustment circuit.

2 . A structure comprising:

a substrate comprising a multilayer structure including a first plurality of layers, the first plurality of layers being stacked perpendicular to a surface of the substrate, each of the first plurality of layers being made of an insulator or a semi-insulating semiconductor;

a first high-frequency line disposed in the substrate, the first high-frequency line being disposed in a first layer of the first plurality of layers;

a second high-frequency line disposed in the substrate, the second high-frequency line having an extension direction different from an extension direction of the first high-frequency line, the second high-frequency line extending through the first plurality of layers; and

a connecting part connecting the first high-frequency line to the second high-frequency line and comprising a bend in an extension direction of the connecting part,

wherein the substrate defines N first spaces on an outer peripheral side of the connecting part, and M second spaces on an inner peripheral side of the connecting part,

wherein the N first spaces and the M second spaces are formed by removing a part of the substrate,

wherein M and N are each an integer of 1 or more,

wherein a relationship MEN is satisfied, and

wherein the N first spaces and the M second spaces expose at least one of the first high-frequency line or the second high-frequency line or are disposed at a position adjacent to at least one of the first high-frequency line or the second high-frequency line, and the N first spaces and the M second spaces are configured to provide an inductive adjustment.

3 . A structure comprising:

a substrate comprising a multilayer structure including a first plurality of layers, the first plurality of layers being stacked perpendicular to a surface of the substrate, each of the first plurality of layers being made of an insulator or a semi-insulating semiconductor;

a first high-frequency line disposed in the substrate, the first high-frequency line being disposed in a first layer of the first plurality of layers;

a second high-frequency line disposed in the substrate, the second high-frequency line having an extension direction different from an extension direction of the first high-frequency line, the second high-frequency line extending through the first plurality of layers; and

a connecting part connecting the first high-frequency line to the second high-frequency line and comprising a bend in an extension direction of the connecting part,

wherein the substrate defines N first spaces on an outer peripheral side of the connecting part, and M second spaces on an inner peripheral side of the connecting part,

wherein the N first spaces and the M second spaces are formed by removing a part of the substrate,

wherein M and N are each an integer of 1 or more; and

a relationship MEN is satisfied.

4 . The structure according to claim 3 , wherein:

a total volume of the M second spaces is smaller than a total volume of the N first spaces.

5 . The structure according to claim 3 ,

wherein the first high-frequency line and the second high-frequency line are any one of a microstrip line, a coplanar line, or a strip line.

6 . The structure according to claim 3 , wherein:

the first high-frequency line is a strip line; and

the second high-frequency line is a pseudo-coaxial line comprising a signal via that penetrates the substrate and a ground plane surrounding the signal via; and

the substrate fills a gap between the signal via and the ground plane.

7 . The structure according to claim 6 , wherein:

the M second spaces expose the ground plane or are disposed at a position adjacent to the ground plane;

the ground plane is disposed in the substrate around both signal lines of the first high-frequency line and the second high-frequency line; and

the N first spaces expose the first high-frequency line at a position adjacent to the second high-frequency line via the substrate.

8 . The structure according to claim 3 ,

wherein the N first spaces and the M second spaces are filled with an insulator having a dielectric constant smaller than a dielectric constant of the substrate or filled with a semi-insulating semiconductor having a dielectric constant smaller than the dielectric constant of the substrate.

9 . The structure according to claim 3 , wherein:

the N first spaces are filled with a first insulator having a dielectric constant smaller than a dielectric constant of the substrate or filled with a first semi-insulating semiconductor having a dielectric constant smaller than the dielectric constant of the substrate;

the M second spaces are filled with a second insulator having a dielectric constant smaller than a dielectric constant of the substrate or filled with a second semi-insulating semiconductor having a dielectric constant smaller than the dielectric constant of the substrate; and

the dielectric constant of the first insulator or the dielectric constant of the first semi-insulating semiconductor in the N first spaces is smaller than the dielectric constant of the second insulator or the dielectric constant of the second semi-insulating semiconductor in the M second spaces.

10 . The structure according to claim 3 ,

wherein the M second spaces are formed by removing a part of a second layer of the first plurality of layers, and the second layer is different from the first layer in which the first high-frequency line is disposed.