Amplifier with multiple, differential input pairs
An amplifier includes a first differential input pair of transistors having a first input terminal, a second input terminal, a first output terminal, and a second output terminal. A second differential input pair of transistors has a third input terminal, a fourth input terminal, a third output terminal, and a fourth output terminal. The first input terminal is coupled to the third input terminal, the second input terminal is coupled to the fourth input terminal, the first output terminal is coupled to the third output terminal, and the second output terminal is coupled to the fourth output terminal. A cross-over circuit has a control input coupled to the second fourth input terminals. The cross-over circuit is configured to vary an amount of bias current through the second differential input pair of transistors based on a magnitude of a voltage on the second and fourth input terminals.
1 . An amplifier, comprising:
a first differential input pair of transistors having a first input terminal, a second input terminal, a first output terminal, and a second output terminal;
a second differential input pair of transistors having a third input terminal, a fourth input terminal, a third output terminal, and a fourth output terminal, the first input terminal coupled to the third input terminal, the second input terminal coupled to the fourth input terminal, the first output terminal directly connected to the third output terminal, and the second output terminal directly connected to the fourth output terminal; and
a cross-over circuit having a control input coupled to the second and fourth input terminals, the cross-over circuit capable of varying an amount of bias current through the second differential input pair of transistors based on a magnitude of a voltage on the second and fourth input terminals.
2 . The amplifier of claim 1 , wherein the first differential input pair of transistors comprises a pair of bipolar junction transistors.
3 . The amplifier of claim 2 , wherein the second differential input pair of transistors comprises a pair of field effect transistors.
4 . The amplifier of claim 3 , wherein the pair of field effect transistors are natural field effect transistors.
5 . The amplifier of claim 1 , wherein:
the first differential input pair of transistors comprises a pair of NPN bipolar junction transistors; and
the second differential input pair of transistors comprises a pair of natural n-channel field effect transistors.
6 . The amplifier of claim 5 , further comprising a third differential input pair of transistors comprising a pair of p-channel field effect transistors.
7 . The amplifier of claim 1 , wherein the cross-over circuit includes:
a first transistor having first control input, the first control input coupled to the second and fourth input terminals;
a first current mirror coupled to the first transistor, the first current mirror capable of producing a first current responsive to a voltage on the second and fourth input terminals;
a second current mirror coupled to the second differential input pair of transistors; and
a current source circuit coupled to the first and second current mirrors.
8 . The amplifier of claim 7 , wherein the current source circuit is capable of providing current to the second current mirror, and an amount of current provided to the second current mirror varies inversely to the first current.
9 . The amplifier of claim 7 , further including:
a second transistor having a fifth control input and first and second current terminals, the first current terminal coupled to the first differential input pair of transistors, the fifth control input coupled to the cross-over circuit, and the second transistor capable of providing a bias current through the first differential input pair of transistors; and
a clamp circuit coupled to the first current terminal.
10 . The amplifier of claim 9 , wherein the clamp circuit is capable of causing the second transistor to operate in a saturation region when the first differential input pair of transistors are off.
11 . The amplifier of claim 7 , further including:
a third differential input pair of transistors having a fifth input terminal, a sixth input terminal, a fifth output terminal, and a sixth output terminal, the fifth input terminal coupled to the first and third input terminals, the sixth input terminal coupled to the second and fourth input terminals, the fifth output terminal coupled to the first and third output terminals, and the sixth output terminal coupled to the second and fourth output terminals.
12 . An apparatus, comprising:
a transistor having a control input and first and second current terminals, the second current terminal being an output of the apparatus;
an amplifier having a reference voltage input, a second input coupled to the output of the apparatus, and an amplifier output, the amplifier output capable of providing a signal to the control input, the amplifier comprising:
a first differential input pair of transistors having a first input terminal, a second input terminal, a first output terminal, and a second output terminal;
a second differential input pair of transistors having a third input terminal, a fourth input terminal, a third output terminal, and a fourth output terminal, the first input terminal coupled to the third input terminal and to the reference voltage input, the second input terminal coupled to the fourth input terminal and to the second current terminal; and
a cross-over circuit having a control input coupled to the second and fourth input terminals, the cross-over circuit capable of varying an amount of bias current through the second differential input pair of transistors based on a magnitude of a voltage on the second and fourth input terminals.
13 . The apparatus of claim 12 , wherein:
the first differential input pair of transistors comprises a pair of NPN bipolar junction transistors; and
the second differential input pair of transistors comprises a pair of natural n-channel field effect transistors.
14 . The apparatus of claim 13 , further comprising a third differential input pair of transistors comprising a pair of p-channel field effect transistors.
15 . The apparatus of claim 12 , wherein the cross-over circuit includes:
a first transistor having first control input, the first control input coupled to the second and fourth input terminals;
a first current mirror coupled to the first transistor, the first current mirror capable of producing a first current responsive to a voltage on the second and fourth input terminals;
a second current mirror coupled to the second differential input pair of transistors; and
a current source circuit coupled to the first and second current mirrors.
16 . The apparatus of claim 15 , wherein the current source circuit is capable of providing current to the second current mirror, and an amount of current provided to the second current mirror varies inversely to the first current.
17 . The voltage regulator of claim 15 , further including:
a third differential input pair of transistors having a fifth input terminal, a sixth input terminal, a fifth output terminal, and a sixth output terminal, the fifth input terminal coupled to the first and third input terminals, the sixth input terminal coupled to the second and fourth input terminals, the fifth output terminal coupled to the first and third output terminals, and the sixth output terminal coupled to the second and fourth output terminals.
18 . The apparatus of claim 17 , further including:
a first transistor coupled to the first differential input pair of transistors, the first transistor having a fifth control input and first and second current terminals, and the first transistor capable of providing a bias current through the first differential input pair of transistors; and
a clamp circuit coupled to the fifth control input and to the first current terminal, the clamp circuit capable of causing the first transistor to operate in a saturation region when the first differential input pair of transistors are off.
19 . The apparatus of claim 12 , wherein the first output terminal is coupled to the third output terminal, and the second output terminal is coupled to the fourth output terminal.
20 . The voltage regulator of claim 19 , wherein the first output terminal is directly connected to the third output terminal, and the second output terminal is directly connected to the fourth output terminal.
21 . An amplifier, comprising:
a first differential input pair of bipolar junction transistors having a first input terminal, a second input terminal, a first output terminal, and a second output terminal;
a second differential input pair of field effect transistors having a third input terminal, a fourth input terminal, a third output terminal, and a fourth output terminal, the first input terminal coupled to the third input terminal, the second input terminal coupled to the fourth input terminal, the first output terminal coupled to the third output terminal, and the second output terminal coupled to the fourth output terminal; and
a cross-over circuit having a control input coupled to the second and fourth input terminals, the cross-over circuit capable of varying an amount of bias current through the second differential input pair of field effect transistors based on a magnitude of a voltage on the second and fourth input terminals.
22 . The amplifier of claim 21 , wherein the cross-over circuit includes:
a first transistor having first control input, the first control input coupled to the second and fourth input terminals;
a first current mirror coupled to the first transistor, the first current mirror capable of producing a first current responsive to a voltage on the second and fourth input terminals;
a second current mirror coupled to the second differential input pair of transistors; and
a current source circuit coupled to the first and second current mirrors.
23 . The amplifier of claim 22 , further comprising:
a third differential input pair of field effect transistors having a fifth input terminal, a sixth input terminal, a fifth output terminal, and a sixth output terminal, the fifth input terminal coupled to the first and third input terminals, the sixth input terminal coupled to the second and fourth input terminals, the fifth output terminal coupled to the first and third output terminals, and the sixth output terminal coupled to the second and fourth output terminals.
24 . The amplifier of claim 23 , further including:
a second transistor having a fifth control input and first and second current terminals, the first current terminal coupled to the first differential input pair of bipolar junction transistors, the fifth control input coupled to the cross-over circuit, and the second transistor capable of providing a bias current through the first differential input pair of bipolar junction transistors; and
a clamp circuit coupled to the first current terminal, the clamp circuit is capable of causing the first transistor to operate in a saturation region when the first differential input pair of bipolar junction transistors are off.
25 . The amplifier of claim 24 , wherein the circuit is capable of varying the amount of bias current through the second differential input pair of field effect transistors in an inverse relationship to the magnitude of a voltage on the second and fourth input terminals.